Polar Code Decoder Architecture for Parallel LLR Pipeline Decoding
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Solution Overview
Problem
Current polar decoders are inefficient in decoding long codewords and lack flexibility to adapt to various codeword types and lengths, leading to high power consumption and hardware complexity issues.
Innovation Solution
A polar code decoder architecture that includes a master and slave processing module system, utilizing logarithmic likelihood ratio (LLR) distribution and partial sum processing units to efficiently decode codewords of varying lengths and types, with a reduced number of hardware units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional polar decoding techniques are used for long codewords, then decoding accuracy is maintained, but decoding time increases significantly
Solution Approach 1:
The patent divides the polar decoding process into multiple parallel processing pipelines, each handling a portion of the codeword. The LLR distributor splits incoming LLR values across multiple PDMs that operate simultaneously, enabling parallel processing of long codewords without sacrificing accuracy, thus reducing overall decoding time while maintaining decoding performance.
Solution Approach 2:
The patent introduces a multi-dimensional processing architecture with master and slave PDMs operating in parallel dimensions. This spatial parallelism allows the system to process multiple segments of the codeword simultaneously across different processing units, effectively transforming the time-consuming sequential decoding into concurrent parallel operations.
2Productivity
If UDPPD technique is used to process single codeword type, then throughput is improved, but flexibility to handle various codeword types is lost
Solution Approach 1:
The patent designs a universal polar decoder architecture where the same PDM hardware can process multiple codeword types by configuring the number of processing pipelines and LLR distribution patterns. The system maintains high throughput for specific codeword types while adapting to various codeword lengths and configurations through programmable control, eliminating the need for separate dedicated decoders for each codeword type.
Solution Approach 2:
The patent implements dynamic configurability in the decoder architecture, allowing the system to adjust the number of active PDMs, pipeline depths, and LLR distribution strategies based on the incoming codeword characteristics. This dynamic adaptation enables the decoder to optimize throughput for different codeword types while maintaining a single flexible hardware platform.
3Adaptability or versatility
If multiple UDPPDs are combined to support various codeword types, then adaptability is improved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent creates a single universal polar decoder that can handle various codeword types through configurable parameters rather than requiring multiple dedicated UDPPD units. By sharing common hardware resources (LLR distributors, PDMs, combiners) across different codeword type configurations, the system achieves multi-type support with significantly reduced hardware complexity and power consumption compared to combining multiple specialized decoders.
4Productivity
If more processing units are added to increase throughput, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent segments the processing workload across multiple PDMs that can be dynamically activated or deactivated based on the required throughput and codeword length. This segmentation allows the system to scale power consumption proportionally with actual processing needs rather than continuously operating all processing units at full power, achieving high throughput when needed while conserving energy during lower-demand operations.
Data Source
AI summary
The disclosed structures and methods are directed to polar code decoders and methods for polar code decoding. A polar code decoder comprises an input logarithmic likelihood ratio (LLR) distributor, a master polar decoder module (PDM), at least one slave PDM, an intermediate LLR result combiner, and a decoded bit aggregator configured to generate a decoded codeword bit sequence. For each codeword node, each PDM partially decodes one or more sets of LLR subsets, which are sent to the intermediate LLR result combiner to generate an intermediate LLR result sequence. A first node decoding pipeline of the master PDM is configured to decode an intermediate LLR result sequence to generate at least one decoded node bit sequence. A polar code decoder with slave PDMs each having a second node decoding pipeline is also disclosed. A method for polar code decoding is also disclosed.