Polar Decoder LLR Computation With Single-Adder Multi-Stage Processing
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Solution Overview
Problem
Existing polar decoders suffer from poor hardware efficiency and high memory bandwidth requirements due to limited parallelism and complex data dependencies, leading to increased latency and hardware resource usage.
Innovation Solution
A novel polar decoder architecture that processes several consecutive stages simultaneously, allowing for full exploitation of parallelism and reducing memory requirements by storing data only at the interfaces between stage groupings, rather than individual stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polar decoder processes stages sequentially with dedicated hardware for each XOR operation, then decoding accuracy is maintained, but hardware efficiency deteriorates and latency increases
Solution Approach 1:
The patent combines multiple consecutive stages of the polar decoder into a single processing unit. This processing unit integrates multiple XOR operations and LLR computations that would traditionally be performed separately in dedicated hardware stages. By merging these operations, the patent reduces the total number of hardware components while maintaining decoding accuracy, thereby improving hardware efficiency and reducing latency.
Solution Approach 2:
The processing unit is designed to perform multiple functions: it executes XOR operations, computes LLR values, and processes multiple consecutive stages within a single clock cycle. This multi-functional design eliminates the need for separate dedicated hardware for each stage, allowing the same hardware resources to be reused across multiple decoding operations, thus improving productivity without proportionally increasing device complexity.
2Ease of operation
If polar decoder stores LLR data at each individual stage interface, then data accessibility is improved, but memory bandwidth requirements increase and hardware efficiency decreases
Solution Approach 1:
The patent merges multiple stage interfaces into a single unified interface for data storage and retrieval. Instead of maintaining separate memory interfaces for each stage, the processing unit accesses LLR data through one consolidated interface, reducing the total memory bandwidth required. This approach maintains data accessibility while significantly lowering memory bandwidth consumption and improving hardware efficiency.
3Loss of time
If polar decoder uses limited parallelism in processing stages, then hardware complexity is reduced, but latency increases and productivity decreases
Solution Approach 1:
The patent combines multiple processing operations that would traditionally require separate parallel hardware units into a single integrated processing unit. This unit performs multiple XOR operations and LLR computations simultaneously within one clock cycle, achieving parallelism without requiring multiple independent hardware paths. This approach reduces latency and improves productivity while avoiding the complexity of extensive parallel hardware.
4Productivity
If polar decoder processes multiple consecutive stages simultaneously, then productivity is improved and latency reduced, but the requirement for flexible hardware reconfiguration increases
Solution Approach 1:
The processing unit is designed with dynamic reconfiguration capabilities, allowing it to adapt its internal operation based on the specific decoding requirements. The unit can be configured to process different numbers of consecutive stages and adjust its computation patterns dynamically. This dynamic design enables high productivity through simultaneous multi-stage processing while maintaining the flexibility needed for various polar code configurations and channel conditions.
Data Source
AI summary
A polar decoder kernal is described. The polar decoder kernal includes a processing unit having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR; a logic circuit configured to manipulate the at least one input LLR; and at least one output configured to output the manipulated at least one LLR. The logic circuit of the processing unit includes only a single two-input adder to manipulate the at least one input LLR, and the input LLR and manipulated LLR are in a format of a fixed-point number representation that comprises a two's complement binary number and an additional sign bit.