Polar Decoder Notation Transformation for Lower-Complexity 5G Decoding
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Solution Overview
Problem
Polar decoders for 5G channels face challenges in reducing hardware complexity and power consumption due to intrinsic latency, often requiring large circuit areas and high power usage to achieve short decoding latency.
Innovation Solution
The method involves transforming input signals from 2's complement notation to signed magnitude notation and using this transformation to perform polar decoding with reduced circuit complexity by employing first and second sub-operation modules with dedicated sign and magnitude processing circuits, thereby optimizing the polar decoding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If advanced wafer fabrication, high operating voltage, or extremely complicated circuit structure is utilized to meet speed requirement, then decoding speed is improved, but power consumption and circuit area are greatly increased
Solution Approach 1:
The patent changes the numerical representation parameter from 2's complement to signed magnitude notation. This parameter change fundamentally alters how arithmetic operations are performed in the decoder circuit, enabling simpler logic circuits that don't require complex carry propagation mechanisms, thus reducing circuit complexity while maintaining decoding speed
Solution Approach 2:
The patent replaces complex mechanical/combinational logic circuits with simpler sequential logic circuits that operate on signed magnitude notation. The substitution transforms the underlying operational mechanism from complex parallel carry-lookahead adders to simpler sequential processing units, reducing hardware complexity
2Speed
If advanced wafer fabrication, high operating voltage, or extremely complicated circuit structure is utilized to meet speed requirement, then decoding speed is improved, but power consumption is greatly increased
Solution Approach 1:
By changing the numerical representation parameter to signed magnitude notation, the patent enables use of simpler logic gates and fewer transistors per operation. This parameter change directly reduces the number of switching elements that consume power, thereby reducing overall power consumption while maintaining decoding speed requirements
Solution Approach 2:
The patent extracts and eliminates the complex carry propagation logic that is inherent in 2's complement arithmetic. By removing this unnecessary complexity for the specific decoding operations required, the circuit uses fewer active components, which directly reduces dynamic power consumption
3Loss of time
If sub-circuits for executing repeated operations are designed with high speed, then decoding latency is reduced, but circuit area is greatly increased
Solution Approach 1:
The patent changes the arithmetic representation parameter to signed magnitude, which allows repeated operations (such as addition and comparison) to be performed with simpler circuit logic. This parameter change enables the same operational speed to be achieved with significantly reduced circuit area, as the simpler logic requires fewer transistors and less interconnect
Data Source
AI summary
A method for performing polar decoding with aid of notation transformation and associated polar decoder are provided. The method includes: transforming input signals from a 2's complement notation to a signed magnitude notation to generate transformed input signals, wherein during the polar decoding, a plurality of first sub-operations and a plurality of second sub-operations are performed to generate decoding results of the transformed input signals; performing a first sign processing to generate a sign result of a first sub-operation within the plurality of first sub-operations; performing a first magnitude processing to generate a magnitude result of the first sub-operation within the plurality of first sub-operations; performing a second sign processing to generate a sign result of a second sub-operation within the plurality of second sub-operations; and performing a second magnitude processing to generate a magnitude result of the second sub-operation within the plurality of second sub-operations.