Polar Decoder Queue Arbitration for Lower-Latency Codeword Processing
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Solution Overview
Problem
Successive Cancellation (SC) polar decoding has low resource utilization and high latency due to serial operation and conditional branching, leading to inefficiencies in processing multiple codewords and increased latency in decoding.
Innovation Solution
A data processing kernel with a queue manager and arbiter system is implemented to manage tokens and buffer access, allowing for interlaced processing of codewords and decoupling conditional decision points, thereby improving resource utilization and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If Successive Cancellation (SC) polar decoding is used, then decoding can be performed with simple circuit structure, but resource utilization is low and latency is high due to serial operation and conditional branching
Solution Approach 1:
The decoding process is segmented into multiple independent processing pipelines, where each pipeline handles a portion of the codeword processing. Multiple codewords are divided and processed in parallel through separate datapath pipelines, transforming the single serial SC decoding into multiple concurrent decoding operations, thereby improving resource utilization while maintaining the fundamental SC decoding structure
Solution Approach 2:
The patent transitions from one-dimensional serial processing to multi-dimensional parallel processing by introducing multiple datapath pipelines that operate simultaneously. This dimensional expansion allows multiple codewords to be processed in parallel through interlaced processing, fundamentally changing the processing architecture from serial to semi-parallel while keeping the circuit structure manageable
2Device complexity
If Successive Cancellation (SC) polar decoding is used, then decoding can be performed with simple circuit structure, but latency is high due to serial operation and conditional branching
Solution Approach 1:
The decoding process is segmented into multiple independent processing pipelines, where each pipeline handles a portion of the codeword processing. Multiple codewords are divided and processed in parallel through separate datapath pipelines, transforming the single serial SC decoding into multiple concurrent decoding operations, thereby improving resource utilization while maintaining the fundamental SC decoding structure
Solution Approach 2:
The arbiter pre-allocates and manages buffer resources before decoding operations begin, establishing a ready-state infrastructure that enables immediate parallel processing. Control signals and buffer allocations are prepared in advance, allowing multiple datapath pipelines to commence processing without sequential waiting, thus reducing overall decoding latency
3Productivity
If interlaced processing of multiple codewords is implemented, then throughput is improved, but device complexity increases due to queue manager and arbiter system
Solution Approach 1:
The queue manager and arbiter system are designed as universal control components that manage multiple datapath pipelines simultaneously. These control circuitry elements perform multiple functions including token management, buffer allocation, and pipeline coordination across all parallel decoding operations, reducing the need for separate control logic for each pipeline and thereby limiting the increase in overall device complexity
Solution Approach 2:
The queue manager acts as an intermediary layer between the input interface and multiple datapath pipelines, buffering and managing tokens that represent decoding operations. This intermediary structure decouples the complexity of parallel pipeline management from the core decoding logic, allowing throughput improvement while containing complexity growth through centralized token-based control
4Productivity
If conditional branching is removed through decoupling, then resource utilization improves, but control complexity increases due to arbiter and buffer management
Solution Approach 1:
Conditional branching logic is extracted and removed from the datapath pipelines, with the arbiter taking over the decision-making function. The arbiter externally manages buffer access and pipeline scheduling based on decoded tokens, separating the control logic from the data processing paths. This extraction improves resource utilization within pipelines while consolidating control complexity in the arbiter component
Data Source
AI summary
Apparatus and method relates generally to data processing kernel. In such an apparatus, a datapath pipeline is configured to process datasets interlaced with respect to one another for multiple passes through a loop with conditional or data dependent decision points. A queue manager is configured with control circuitry sets to provide an instruction interface to the datapath pipeline. Each of the control circuitry sets includes: a first buffer and a second buffer each configured to buffer tokens for correspondence with the datasets. Each of the control circuitry sets further includes: an arbiter configured to decouple the conditional or data dependent decision points from the datapath pipeline to selectively provide access of the first buffer or the second buffer to the datapath functions. Memory is configured to provide access to and storage of the datasets to the datapath pipeline.