Polar Decoder Architecture With Stored Reliability Sequences

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Solution Overview

Problem

Existing polar decoders for 5G NR PUCCH face inefficiencies in resource utilization, particularly in the use of look-up tables (LUTs) and flip-flops when implemented on RFSoC, necessitating a more efficient decoder system.

Innovation Solution

A Field Programmable Gate Array (FPGA) implementation of a polar decoder that includes a core block with pre-calculated reliability sequences and a CRC module, optimizing decoding through successive cancellation and list decoding with reduced resource consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a polar decoder is implemented on RFSoC using conventional methods, then decoding functionality is achieved, but resource utilization becomes inefficient with high consumption of LUTs and flip-flops

Engineering Contradiction:
Improvedecoding functionalityVSAvoidresource consumption (LUTs and flip-flops)
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent pre-calculates and stores reliability sequences (bitmaps) before decoding operations. These pre-computed sequences are stored in memory and retrieved during decoding, eliminating the need for complex real-time calculations and reducing LUT requirements by 96.8% compared to conventional implementations

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses stored bitmap copies of reliability sequences instead of performing complex calculations during decoding. The bitmaps serve as simplified representations that can be quickly referenced, replacing resource-intensive computational structures with lightweight data storage and retrieval operations

Inventive Principle:
Principle #26Copying

2Measurement precision

If reliability sequences are calculated in real-time during decoding, then accurate decoding is achieved, but computational complexity and resource usage increase significantly

Engineering Contradiction:
Improvedecoding accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Reliability sequences are pre-calculated offline and stored as bitmaps in memory. During actual decoding operations, these pre-computed sequences are simply retrieved and applied, maintaining decoding accuracy while eliminating real-time computational complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces the mechanical/computational process of real-time reliability calculation with a data retrieval process. Complex computational operations are substituted with simple memory read operations, dramatically reducing resource consumption while preserving decoding precision

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20260012205A1System and method for polar decoding
Publication Date: 2026.01.08 JIO PLATFORMS LTD
  • US20260012205A1 patent drawing
  • US20260012205A1 patent drawing
  • US20260012205A1 patent drawing

AI summary

The present disclosure provides a system and method for polar decoding in a communication system. A polar decoder includes a core block including a successive cancellation decoder and a list decoder, and a cyclic redundancy check (CRC) module, wherein the core block stores one or more pre-calculated reliability sequence for decoding the received encoded data bits.