Polar Decoder LLR Computation With Single-Adder Stage Parallelism
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Solution Overview
Problem
Existing polar decoder hardware implementations suffer from poor hardware efficiency, high memory bandwidth requirements, and limited parallelism due to data dependencies, leading to increased latency and hardware resource usage, especially in processing stages other than the right-most stage.
Innovation Solution
A polar decoder architecture that processes several consecutive stages in parallel, using a single two-input adder for LLR manipulation and flexible reuse of hardware to perform either 'f' or 'g' functions, reducing hardware complexity and memory requirements by storing LLRs only at interfaces between stage groupings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated hardware is used to compute f-function and g-function at each XOR location in the graph, then the decoding accuracy is improved, but the hardware complexity and memory bandwidth requirements increase significantly
Solution Approach 1:
A single processing element is designed to perform multiple functions: it can compute both f-function and g-function, and it can operate in different modes (adder mode, subtractor mode, selector mode) depending on the operational phase. This universal processing element replaces the need for dedicated hardware at each XOR location, significantly reducing hardware complexity while maintaining decoding accuracy
Solution Approach 2:
The patent merges the computation of f-function and g-function into a unified processing structure. The same processing element that computes f-function is reused to compute g-function by switching its internal operation mode, thereby combining multiple computational functions into a single hardware unit and reducing overall hardware complexity
2Productivity
If LLRs are stored at every stage interface in the graph, then the parallelism is improved, but the memory bandwidth requirements and hardware resource usage increase
Solution Approach 1:
The patent extracts only the essential LLR storage locations from the full stage-interface storage scheme. Instead of storing LLRs at every stage interface, LLRs are stored only at the input of the processing element and at specific intermediate points where data dependency requires persistence. This selective extraction of storage locations reduces memory bandwidth requirements while maintaining necessary parallelism
Solution Approach 2:
The decoding graph is segmented into processing stages, and memory storage is selectively applied only at critical segmentation boundaries where data must be preserved across stage transitions. This segmented approach to memory storage reduces overall memory usage while maintaining parallelism within each stage
3Device complexity
If a single processing element is reused to perform both f-function and g-function, then the hardware complexity is reduced, but the latency increases due to sequential operation
Solution Approach 1:
The processing element operates in periodic cycles, alternating between computing f-function and g-function based on the current operational phase. This periodic switching allows the single processing element to perform both functions systematically, reducing hardware complexity while managing latency through structured time-multiplexed operation
Solution Approach 2:
The processing element is pre-configured with the capability to perform both f-function and g-function computations, and the control logic prepares the appropriate operation mode in advance before each computational phase. This preliminary preparation minimizes reconfiguration overhead and reduces the latency penalty associated with using a single processing element for multiple functions
Data Source
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AI summary
A polar decoder kernal (111) is described. The polar decoder kernal (111) includes a processing unit (2201) having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR, (2202, 2203); a logic circuit configured to manipulate the at least one input LLR; and at least one output configured to output the manipulated at least one LLR. The logic circuit of the processing unit (2201) includes only a single two-input adder (2207) to manipulate the at least one input LLR, and the input LLR and manipulated LLR are in a format of a fixed-point number representation that comprises a two's complement binary number and an additional sign bit.