Polar Encoder Architecture for Low-Latency 5G NR Coding

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Solution Overview

Problem

Current polar encoding techniques for communication systems, particularly in 5G New Radio (NR) standards, face challenges in achieving low latency and high throughput while maintaining low power consumption and area efficiency, especially when implementing polar codes with O(N) space complexity.

Innovation Solution

The development of a polar encoder with O(N) space complexity and a binary progression sequence-based implementation that utilizes a binary counter and decode enable generator, allowing for efficient encoding and decoding operations with reduced latency and power requirements, suitable for FPGA or ASIC implementations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional polar encoding techniques are used, then encoding capability is achieved, but latency and power consumption increase

Engineering Contradiction:
Improveencoding latencyVSAvoidencoder structure complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The encoder is segmented into N independent output stages, each responsible for generating one encoded bit. This segmentation allows parallel processing of multiple bits simultaneously, reducing overall encoding latency while maintaining manageable complexity at each stage through the use of binary counters and decode enable generators.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The encoder employs dynamic enable signals that are generated based on binary counter values. These enable signals dynamically control which output stages are active at any given time, allowing the encoder to adapt its operation to the specific code size N and optimize performance for different encoding scenarios.

Inventive Principle:
Principle #15Dynamics

2Area of stationary object

If O(N) space complexity polar codes are implemented, then area efficiency is improved, but encoding throughput may be limited

Engineering Contradiction:
Improveencoder areaVSAvoidencoding throughput
Core Design Contradiction:
Area of stationary objectVSProductivity

Solution Approach 1:

The encoder architecture is divided into N independent output stages that can operate in parallel. Each stage processes one bit of the encoded output, allowing the throughput to scale linearly with the number of stages while maintaining O(N) space complexity. This segmentation enables high-speed parallel encoding without requiring quadratic space.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The binary counter and decode enable generator are universal components that can be reused across all N output stages. These components generate the necessary control signals for any code size N, making the encoder architecture universally applicable and efficient for various polar code configurations without requiring separate dedicated hardware for each stage.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If complex polar decoding is performed, then decoding accuracy is improved, but power consumption increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoiddecoder power consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The decoding process is segmented into successive cancellation stages, where each stage processes one bit independently based on previously decoded bits. This segmentation allows the decoder to achieve high accuracy through systematic error correction while consuming less power by avoiding more complex iterative decoding algorithms that would require additional computational resources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The decoder performs preliminary processing by organizing the received signal into a structured format and pre-computing necessary metrics before the main decoding process. This preliminary action prepares the data in an optimal form for successive cancellation decoding, improving accuracy while minimizing the computational power required during the actual decoding operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11569845B2Polar encoding and polar decoding systems and methods
Publication Date: 2023.01.31 INTEL CORP
  • US11569845B2 patent drawing
  • US11569845B2 patent drawing
  • US11569845B2 patent drawing

AI summary

In encoding systems and methods, data or information is encoded using one or more encoding methodologies to generate encoded data or information corresponding to the data or information. Similarly, in decoding systems and methods, encoded data or information is decoded using one or more decoding methodologies to generate the data or information corresponding to the encoded data or information. The encoding/decoding systems and methods can include polar encoding/decoding systems and methods operable for encoding data or information to generate polar codes and for decoding polar codes to generate the corresponding data or information. The information or data can be control information and application data for communication over networks. The networks can include wireless and wireline networks, and network segments, links or channels, including mixed wireline and wireless networks.