Polar Encoder Kernel Layout for Variable Block Size Encoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing polar encoders face inefficiencies in hardware utilization and critical path length due to their design dependency on the maximum number of stages in the polar code graph, leading to suboptimal performance for varying block sizes and unused hardware when encoding short blocks.
Innovation Solution
The proposed polar encoder kernel decomposes the polar code graph into columns with varying stages, allowing each column to be processed independently, optimizing hardware usage and reducing critical path length, enabling efficient encoding across different block sizes by configuring the datapath to utilize all hardware in every step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the polar encoder is designed to support the maximum number of stages n_max = log2(Nmax), then it can encode long blocks, but hardware efficiency deteriorates when encoding short blocks due to unused hardware
Solution Approach 1:
The patent segments the polar code graph into multiple columns, where each column contains a subset of the total stages. The encoder can selectively activate only the columns needed for the current block size, rather than activating all columns designed for maximum block size. This segmentation allows the hardware to be divided into independent functional units that can be dynamically enabled or disabled based on the encoding requirements.
Solution Approach 2:
The patent implements dynamic configuration of the encoder by allowing the number of active columns to vary based on the block size being encoded. The system transitions from a static design where all columns are always active to a dynamic design where the active column count adapts to the specific encoding task, optimizing hardware utilization for each operation.
2Adaptability or versatility
If the encoder uses a fixed datapath configured for n_max stages, then it can handle long blocks, but the critical path length increases unnecessarily for short blocks
Solution Approach 1:
The critical path is segmented into multiple column segments, each with its own stage count. By activating only the necessary number of columns for a given block size, the effective critical path length is reduced proportionally. For example, encoding a short block may only require 2 out of 4 columns, halving the critical path length and doubling the achievable clock frequency.
Solution Approach 2:
The patent changes the operational parameters of the encoder by dynamically adjusting the number of active columns based on block size. This parameter change directly affects the critical path length, allowing the system to optimize speed for each encoding operation by configuring the active hardware resources to match the minimum necessary for the task.
3Device complexity
If columns are processed sequentially one after another, then hardware complexity is reduced, but the number of clock cycles increases
Solution Approach 1:
The patent segments the processing into independent column units that can be executed in parallel. Each column represents an independent processing stage with no data dependencies on other columns, enabling simultaneous execution. This segmentation transforms the processing from a strictly sequential model to a parallel model, reducing total execution time while maintaining manageable hardware complexity within each column.
Solution Approach 2:
The patent merges multiple independent column operations into a single parallel execution cycle. By combining the processing of multiple columns that can operate simultaneously, the system achieves higher throughput without proportionally increasing hardware complexity, as each column uses a standardized, reusable structure.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A polar encoder kernal (102) is described. The polar encoder kernal (102) is configured to receive one or more bits from a kernal information block (105) having a kernal block size of N; and output one or more bits from a kernal encoded block (106) having a block size that matches the kernal block size N; wherein the polar encoder kernal (102) comprises a decomposition of a polar code graph having multiple columns (702) and where each column is further decomposed into one or more polar code sub-graphs (701) and is configured to process encoded bits one polar code subgraph (701) at a time.