Polar Encoder Reliability Mapping for RFSoC Resource Constraints
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Solution Overview
Problem
Existing polar encoders implemented on RFSoC face resource utilization challenges and require run-time support for data combinations, limiting their efficiency in 5G NR PDCCH applications.
Innovation Solution
A Field Programmable Gate Array (FPGA) implementation of a polar encoder with pre-stored reliability sequences and modules like CRC attachment, interleaver, and frozen bit mapper, optimizing resource usage by eliminating the need for bit array tables and reducing PS-PL interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If polar encoder is implemented on RFSoC with run-time data combination support, then coding scheme functionality is maintained, but resource utilization increases and efficiency decreases
Solution Approach 1:
The patent pre-calculates and stores reliability sequences for all possible data combination configurations in lookup tables before runtime. The frozen bit mapper module fetches pre-computed reliability sequences based on control information parameters (k, N, L) without performing real-time calculations. This preliminary computation approach eliminates the need for complex run-time processing logic while maintaining support for multiple data combinations, thereby reducing resource utilization and improving encoding efficiency.
2Manufacturing precision
If bit array tables are generated and pushed from PS to PL, then encoding accuracy is maintained, but interface complexity and resource usage increase
Solution Approach 1:
The patent extracts only the essential reliability sequence data needed for polar encoding from the complex bit array table structure. Instead of transferring complete bit array tables from the programmable system (PS) to programmable logic (PL) through complex interfaces, the design extracts and stores only the critical reliability sequence information in lookup tables within the PL. This extraction approach maintains encoding accuracy by preserving the essential mapping relationships while eliminating redundant data transfer overhead and simplifying the PS-PL interface requirements.
Data Source
AI summary
The present disclosure provides a system and method for polar encoding in a communication system. A polar encoder includes a cyclic redundancy check (CRC) attachment module, an interleaver, a frozen bit mapper, and a polar transformer. The frozen bit mapper receives a master block comprising payload data and control information from the interleaver and fetches a pre-stored reliability sequence based on the control information in the master block to generate an encoded word.