Polar Decoder Graph Decomposition for Low-Latency Parallel Decoding
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Solution Overview
Problem
Existing polar decoder hardware implementations suffer from poor hardware efficiency, high memory bandwidth requirements, and limited parallelism due to data dependencies, leading to increased latency and reduced throughput in polar decoding processes.
Innovation Solution
A novel polar decoder architecture that processes several consecutive stages simultaneously, reducing memory requirements and enhancing parallelism, allowing for flexible support of different kernel block sizes and optimizing hardware resource usage by decomposing the polar code graph into columns and rows, enabling efficient partial sum propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polar decoding is performed using conventional hardware implementations with sequential stage processing, then data dependencies are properly managed, but hardware efficiency is poor and latency is increased
Solution Approach 1:
The polar code graph is decomposed into multiple columns, where each column contains a subset of stages. This segmentation allows independent parallel processing of columns while maintaining data dependency constraints within each column, thereby improving hardware efficiency and reducing latency without compromising decoding correctness
Solution Approach 2:
The patent introduces a column-based dimensional organization to the traditional stage-based sequential processing. By arranging stages into columns and processing them in parallel along the column dimension, the system achieves higher throughput while managing data dependencies through careful column ordering and memory organization
2Speed
If memory bandwidth is increased to support higher parallelism, then decoding speed improves, but memory bandwidth requirements become excessively high
Solution Approach 1:
By dividing the polar code graph into columns that can be processed independently, the patent reduces the amount of data that needs to be transferred through memory at any given time. Each column processes a subset of stages with localized data access patterns, thereby reducing overall memory bandwidth requirements while maintaining parallel processing benefits
Solution Approach 2:
The patent processes columns in a staged manner rather than all simultaneously, using partial parallelism that balances throughput requirements with memory bandwidth constraints. This allows the system to achieve improved latency without requiring peak memory bandwidth that would be necessary for full simultaneous column processing
3Productivity
If data dependencies are strictly enforced in sequential order, then decoding accuracy is maintained, but parallelism is limited and throughput is reduced
Solution Approach 1:
The patent segments the polar code graph into columns where data dependencies are contained within each column. This allows columns to be processed in parallel while maintaining the correctness of dependency relationships within each segment, thereby achieving both high throughput and decoding accuracy
Solution Approach 2:
The patent dynamically determines the processing order of columns based on data dependency analysis. By flexibly ordering column processing and allowing adaptive parallelism where dependencies permit, the system maintains decoding accuracy while maximizing throughput potential
4Device complexity
If hardware resources are optimized for fixed block sizes, then hardware efficiency improves, but adaptability to different kernel block sizes is reduced
Solution Approach 1:
The column-based architecture provides a universal framework that can accommodate different kernel block sizes by adjusting the number and configuration of columns. The same hardware structure can be reconfigured to process various block sizes efficiently, achieving both hardware efficiency and adaptability through parameterizable column organization
Data Source
AI summary
A polar decoder kernal is described. The polar decoder kernal is configured to: receive one or more soft bits from a soft kernal encoded block having a block size of N and output one or more recovered kernal information bits from a recovered kernal information block having a block size of N. The polar decoder kernal comprises a decomposition of a polar code graph into an arbitrary number of columns depending on the kernal block size N.