Polar Code Interleaving With Circular-Buffer Bit Selection

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Solution Overview

Problem

Current polar code interleaving and bit selection methods in wireless communication networks face inefficiencies, particularly when the polar code size exceeds the transmission bit size, leading to suboptimal error correction performance and increased complexity in rate matching and bit selection processes.

Innovation Solution

The proposed solution involves a novel approach to polar code interleaving and bit selection, where the polar code is divided into a lower, middle, and upper part, with rate-independent interlaced sub-block interleaving of the middle part and rate-dependent bit selection based on output length, utilizing a unified rate-matching design that includes puncturing, shortening, and repetition operations, and employing a circular buffer for efficient bit access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If polar code size N is increased to improve error correction capability, then reliability is improved, but device complexity increases due to rate matching and bit selection requirements

Engineering Contradiction:
Improveerror correction capabilityVSAvoidrate matching and bit selection complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the polar code block into multiple sub-blocks and applies different interleaving schemes to different segments. The middle part undergoes rate-independent interlaced sub-block interleaving, while bit selection is applied to other segments based on output length requirements. This segmentation allows the system to handle large polar code sizes by processing smaller manageable segments, reducing the complexity of rate matching and bit selection operations.

Inventive Principle:
Principle #1Segmentation

2Reliability

If rate-independent interlaced sub-block interleaving is applied to the middle part, then error correction performance is improved, but processing time increases

Engineering Contradiction:
Improveerror correction performanceVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies rate-independent interlaced sub-block interleving specifically to the middle part of the polar code block, while other parts use different processing. This localized application of interleving to the middle part optimizes error correction performance for that specific segment without requiring the entire code block to undergo the same time-consuming processing, thus balancing performance improvement with processing efficiency.

Inventive Principle:
Principle #3Local quality

3Reliability

If bit selection is performed based on output length to match transmission channel capacity, then transmission quality is improved, but device complexity increases

Engineering Contradiction:
Improvetransmission qualityVSAvoidbit selection processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic bit selection based on the output length E, which is determined by the transmission channel capacity and code rate requirements. The bit selection process adapts to different output length requirements by selectively choosing bits from the interleaved code block. This dynamic approach allows the system to optimize transmission quality for different channel conditions while using a unified rate-matching design that handles puncturing, shortening, and repetition operations efficiently.

Inventive Principle:
Principle #15Dynamics

4Productivity

If polar code is divided into lower, middle, and upper parts with selective interleving, then bit selection efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvebit selection efficiencyVSAvoidinterleaving structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the polar code block into lower, middle, and upper parts, applying rate-independent interlaced sub-block interleving specifically to the middle part. This segmentation strategy improves bit selection efficiency by preparing the middle part in advance with a structure that facilitates efficient bit selection based on output length. The division into segments allows for targeted processing that optimizes the bit selection process while managing complexity through structured organization.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3577769B1Polar code interleaving and bit selection
Publication Date: 2024.04.17 MEDIATEK INC
  • EP3577769B1 patent drawingFigure 1
  • EP3577769B1 patent drawingFigure 2A~2C
  • EP3577769B1 patent drawingFigure 3

AI summary

Apparatus and methods are provided for polar code sub-block interleaving and bit selection. In one novel aspect, middle-part interlaced sub-block interleaving is provided for polar code interleaving. In one embodiment, the middle part of the polar code is interlaced and generates the interleaved polar code. In another embodiment, the lower part and the upper part are also sub-block interleaved with the middle-part interlaced method. In another novel, rate-dependent unified bit selection is provided. The bit selection is categorized into three operation categories of repetition, puncturing and the shortening. Each category follows unified bit selection rule with different categories differ only in the access scheme. In one embodiment, the circular buffer is used for bit selection.