Polar Code Interleaving with Column-Reversal Rate Matching

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Solution Overview

Problem

Current polar code interleaving designs face challenges in combining with rate matching, leading to increased implementation complexity and difficulty in randomizing encoded bits effectively.

Innovation Solution

A method and apparatus that simplify the interleaving process by reading and writing bit sequences in a reversal order, allowing for simultaneous interleaving and rate matching, and sorting encoded bits based on priority orders to facilitate rate matching operations, thereby reducing implementation complexity and enhancing bit randomization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If an interleaving module is added after the rate matching module to implement randomization of encoded bits, then the randomization capability is improved, but the implementation complexity increases

Engineering Contradiction:
Improvebit randomization capabilityVSAvoidimplementation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the interleaving function and rate matching function into a single integrated module. The interleaver is designed to perform both rate matching (selecting M bits from N encoded bits) and interleaving (reordering bits for randomization) simultaneously, eliminating the need for a separate interleaving module after rate matching.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interleaver is designed as a multi-functional device that can perform rate matching, interleaving, and de-interleaving operations. By making the interleaver universal, it handles multiple tasks that were previously required separate modules, thereby reducing overall system complexity while maintaining bit randomization capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a quadratic interleaving operation is used to achieve polar code interleaving, then the interleaving effectiveness is improved, but the implementation complexity increases

Engineering Contradiction:
Improveinterleaving effectivenessVSAvoidimplementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs reverse reading order in the interleaver to achieve interleaving effectiveness. Instead of using complex quadratic interleaving operations, bits are read from the interleaver in reverse order (from bottom to top or right to left), which simplifies the implementation while maintaining the desired error dispersion and randomization effects.

Inventive Principle:
Principle #13The other way round (Inversion)

3Ease of operation

If interleaving and rate matching are performed as separate operations, then the functional clarity is improved, but the implementation complexity increases

Engineering Contradiction:
Improvefunctional clarityVSAvoidimplementation complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges the interleaving operation and rate matching operation into a single integrated process within the interleaver module. The rate matching is performed by selecting M bits from N encoded bits, and the interleaving is simultaneously performed by reading these bits in reverse order, achieving both functions in one step rather than as separate operations.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11245423B2Interleaving method and apparatus
Publication Date: 2022.02.08 HUAWEI TECH CO LTD
  • US11245423B2 patent drawing
  • US11245423B2 patent drawing
  • US11245423B2 patent drawing

AI summary

An interleaving method and apparatus are provided, to reduce complexity of implementation processes of polar code interleaving and rate matching. The method includes: obtaining encoded bits after polar code encoding, and sorting the encoded bits based on a priority order of performing a rate matching operation, to obtain a first bit sequence. The first bit sequence includes j subsequences, and j is a positive integer. The method further includes writing the first bit sequence into an interleaver of i rows and j columns. Bits in a column in the interleaver include one of the j subsequences; and reading out bits from the interleaver column by column, until M bits are read. At least two adjacent columns have opposite readout directions, and M is a target code length.