Non-Linear Polar Multiplier Cell With Floating-Node Reset
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Solution Overview
Problem
Existing multiplier cell designs in complementary metal oxide semiconductor (CMOS) logic require a large number of transistors, leading to high power consumption and area usage, which is a challenge for devices aiming for lower power consumption.
Innovation Solution
Implementing a multiplier cell using non-linear polar material-based majority and minority gates, which include ferroelectric or paraelectric material, and incorporating a reset mechanism to maintain charge balance at the floating node, reducing the need for switching transistors and interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional CMOS logic gates (AND, OR, XOR) are used to build a 1-bit full adder for multiplier cells, then the circuit can perform basic arithmetic operations, but the number of transistors increases leading to high power consumption and large area usage
Solution Approach 1:
The patent changes the fundamental operating parameters by using non-linear polar materials (ferroelectric or paraelectric) instead of traditional CMOS logic. This material substitution enables the circuit to operate with fewer transistors while maintaining computational functionality, directly reducing power consumption and area usage in multiplier cells
Solution Approach 2:
The invention employs composite structures combining non-linear polar materials with traditional semiconductor components. The ferroelectric or paraelectric materials are integrated with metal oxide semiconductor devices to create hybrid logic gates that achieve lower power operation while preserving the necessary logical functions for multiplication operations
2Area of stationary object
If non-linear polar material-based majority and minority gates are used to reduce transistor count, then power consumption and area are reduced, but charge balance at floating nodes must be maintained requiring reset mechanisms
Solution Approach 1:
The reset mechanism is activated in advance during reset phases to pre-establish charge balance at floating nodes before computation begins. This preliminary action ensures that the non-linear polar material-based gates start each operation with proper charge conditions, preventing computational errors while maintaining compact circuit area
Solution Approach 2:
The circuit operates in periodic cycles alternating between computation phases and reset phases. During reset phases, the reset mechanism recharges floating nodes to maintain charge balance, while during computation phases, the compact non-linear polar material gates perform logical operations. This periodic operation enables sustained low-power performance with controlled reset complexity
3Use of energy by moving object
If the circuit is designed for low voltage operation to reduce power consumption, then energy efficiency improves, but signal integrity and noise margin may be compromised
Solution Approach 1:
The non-linear polar materials exhibit sharp switching characteristics at specific voltage thresholds, enabling reliable logic level transitions even at low supply voltages. This parameter change in material behavior allows the circuit to maintain signal integrity and noise margins while operating at reduced voltages for improved energy efficiency
Solution Approach 2:
The ferroelectric or paraelectric materials undergo phase transitions between polar and non-polar states at well-defined voltage thresholds. These abrupt phase transitions create clear digital logic levels with high noise margins, ensuring signal integrity is maintained even when the overall supply voltage is reduced for lower power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in compact, low-power multiplier circuits with reduced interconnect length, allowing for low voltage operation and low power consumption, and enables processors to enter low-power states without data loss, while maintaining high density and functionality.
Implementation Method 1
Implementing a multiplier cell using non-linear polar material-based majority and minority gates, which include ferroelectric or paraelectric material
Implementation Method 2
Implementing a multiplier cell using non-linear polar material-based majority and minority gates, which include ferroelectric or paraelectric material
Implementation Method 3
incorporating a reset mechanism to maintain charge balance at the floating node
Data Source
AI summary
A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.