Non-Linear Polar Multiplier Cell With Shared Reset for Low Power
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Solution Overview
Problem
Conventional multiplier cells in CMOS logic require numerous transistors, leading to increased power consumption and area, which poses challenges in achieving lower power consumption and compact design, especially in battery-powered devices.
Innovation Solution
The use of non-linear polar materials such as ferroelectric or paraelectric materials in majority and minority gates within the multiplier cells, combined with a transmission-gate based reset mechanism, reduces the number of transistors and interconnects, enabling more compact and power-efficient designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional CMOS logic gates (AND, OR, XOR) are used in multiplier cells, then the circuit can perform multiplication operations, but the number of transistors increases leading to increased power consumption and area
Solution Approach 1:
The patent changes the fundamental operating parameter of the logic gates from conventional CMOS switching to non-linear polar material-based majority/minority gate operations. This parameter change enables the same logical functionality (multiplication) to be achieved with fewer transistors, directly resolving the contradiction between power consumption and device complexity
Solution Approach 2:
The patent implements a universal reset mechanism that can reset multiple majority gates simultaneously using shared reset signals and transistors. This multi-functional approach allows a single reset structure to serve multiple logic units, reducing the overall transistor count while maintaining the ability to reset the entire multiplier circuit
2Productivity
If conventional CMOS logic gates are used in multiplier cells, then the circuit can perform multiplication operations, but the area occupied by the circuit increases
Solution Approach 1:
The patent merges multiple logic functions into unified majority gate structures that use non-linear polar materials. By combining the logical operations of conventional AND, OR, and XOR gates into single majority gate units, the circuit achieves the same multiplication productivity with significantly reduced area occupancy
Solution Approach 2:
The transition to non-linear polar material-based gates changes the physical parameter of gate implementation, enabling more compact logic units that perform the same multiplication operations in smaller area, thus resolving the contradiction between productivity and area
3Power
If the number of transistors in multiplier cells is reduced using non-linear polar materials, then power consumption and area are reduced, but a reset mechanism is required to maintain proper operation
Solution Approach 1:
The reset mechanism is designed as a universal structure that can reset all majority gates in the multiplier circuit simultaneously through shared reset signals and transistors. This multi-functional design allows the reset mechanism to serve the entire circuit with minimal additional complexity, resolving the contradiction between power reduction and reset mechanism complexity
Solution Approach 2:
The reset mechanism is designed to automatically reset the majority gates to their initial states without requiring external intervention or complex control logic. By enabling self-resetting functionality, the mechanism maintains proper operation with minimal added complexity while preserving the power and area benefits of the reduced transistor count
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly reduced power consumption and area usage, allowing for the creation of extremely compact multiplier circuitry with intermittent operation capabilities and low voltage switching, which is essential for energy-efficient processors.
Implementation Method 1
The use of non-linear polar materials such as ferroelectric or paraelectric materials in majority and minority gates within the multiplier cells
Implementation Method 2
The use of non-linear polar materials such as ferroelectric or paraelectric materials in majority and minority gates within the multiplier cells
Data Source
AI summary
A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.