Polar Receiver Digital Demodulation Phase Recovery
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Solution Overview
Problem
Polar receiver architectures face poor performance and high bit error rates due to deficiencies in signal processing and architecture, particularly in recovering data from modulated carrier signals without effective carrier recovery circuitry.
Innovation Solution
The polar receiver employs frequency division circuitry, a self-triggered time-to-digital converter, and CORDIC logic to measure and process the phase and amplitude of modulated signals, using harmonic injection-locked oscillators and Vernier time-to-digital converters to extract phase information without external triggers, enabling accurate phase recovery and symbol identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If polar receiver architecture is used to eliminate carrier recovery circuitry, then device complexity is reduced, but measurement precision of phase information deteriorates
Solution Approach 1:
The patent introduces an intermediary carrier signal generated by a voltage-controlled oscillator (VCO) that is modulated by the recovered phase information. This intermediary carrier serves as a mediator between the simplified polar receiver architecture and the precise phase measurement requirement, enabling accurate phase information extraction without complex carrier recovery circuitry by comparing the received signal with this generated carrier signal.
Solution Approach 2:
The patent implements a feedback mechanism where the recovered phase information is used to modulate the VCO output, creating a feedback loop that continuously refines the carrier signal. This feedback allows the system to maintain high measurement precision for phase information by constantly adjusting the generated carrier based on the extracted phase data, compensating for the absence of traditional carrier recovery circuitry.
2Reliability
If digital demodulation is implemented in polar receiver, then reliability of signal recovery is improved, but device complexity increases
Solution Approach 1:
The patent replaces traditional analog signal processing mechanisms with digital demodulation techniques. Instead of using complex analog circuits for signal recovery, the system employs digital signal processing algorithms that operate on the I and Q components extracted from the polar representation. This substitution of mechanical/analog systems with digital ones improves reliability through better noise immunity and processing accuracy while managing complexity through software-based solutions.
Solution Approach 2:
The patent segments the signal processing function into distinct digital processing stages: polar-to-rectangular conversion, separate I and Q component processing, individual demodulation of each component, and final symbol decision. This segmentation allows each stage to be optimized independently, improving overall signal recovery reliability while making the complex processing task more manageable and implementable through modular digital circuits.
3Measurement precision
If frequency division and time-to-digital conversion are used for phase measurement, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent employs periodic action through frequency division, where the incoming carrier signal is divided by a factor N to produce a lower frequency signal. This periodic frequency division allows the use of a time-to-digital converter with relaxed timing requirements while maintaining precise phase measurement capability. The periodic nature of the divided signal enables accurate phase detection through time interval measurement without requiring extremely high-speed digital circuits.
Solution Approach 2:
The patent implements self-service through the use of a self-triggered time-to-digital converter that uses the frequency-divided signal itself as the trigger source. The signal triggers its own conversion process, eliminating the need for external high-precision clock sources or additional trigger circuitry. This self-service mechanism achieves high measurement precision while minimizing the complexity of external support circuits required.
Data Source
AI summary
Circuitry and methods are described for digital signal demodulation. In a polar receiver, a modulated radio-frequency input signal is provided to frequency division circuitry, which may include a harmonic injection-locked oscillator (ILO). The phase of the frequency-divided output is measured using a self-triggered time-to-digital converter (TDC), which may be a Vernier TDC. A subtractor subtracts a period offset from the output of the TDC to generate an offset digital time output, and a digital integrator integrates the offset digital time output. The integrated time signal represents the phase of the radio-frequency input signal and can be used to determine a symbol, such as a phase-shift keying (PSK) or quadrature amplitude modulation (QAM) symbol, conveyed by the modulated radio-frequency input signal.