Polar Code SCL Decoder Memory Split to Cut Multiplexing Cost
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Solution Overview
Problem
Polar code decoders face high latency and inefficient hardware usage due to the high resource cost of multiplexing in successive cancellation list (SCL) decoding, particularly when handling multiple codewords and stages within a common memory system.
Innovation Solution
The implementation of a decoder circuit using two separate memories with independent addressing systems reduces the resource cost for multiplexing, allowing for efficient storage and processing in SCL decoding by separating the update and sort operations across different memory units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a common memory system is used for multiple codewords and stages in SCL decoding, then memory sharing is achieved, but the resource cost for multiplexing increases and hardware efficiency decreases
Solution Approach 1:
The patent divides the common memory system into separate memory units, each dedicated to specific codewords or stages. This segmentation eliminates the need for complex multiplexing while maintaining memory sharing capabilities across different decoding operations, thereby reducing hardware resource cost and improving efficiency.
2Reliability
If list decoding is performed for polar codes, then decoding accuracy is improved, but latency increases and hardware usage becomes inefficient
Solution Approach 1:
The patent performs preliminary organization of data in separate memory units before decoding operations begin. By pre-positioning codeword data and stage information in dedicated memory locations, the decoding process can proceed without delays caused by data retrieval or multiplexing, thus maintaining high decoding accuracy while reducing latency.
3Adaptability or versatility
If multiple decoding stages are handled within a common memory system, then system integration is improved, but hardware resource efficiency decreases
Solution Approach 1:
The patent creates separate memory unit copies for different decoding stages and codewords. Each memory unit contains replicated data structures and control logic, allowing parallel processing of multiple codewords without contention. This copying approach maintains system integration while significantly improving hardware resource efficiency by enabling simultaneous independent operations.
Data Source
AI summary
A decoder circuit includes an input configured to receive an encoded message, and a decoding loop circuit including first and second memories, an update circuit, and a sort circuit. The decoding loop circuit is configured to perform list decoding to the encoded message by successively decoding a plurality of bits of a first codeword of the encoded message in a plurality of decoding loops respectively; and provide, to an output, a decoded message. In each decoding loop, the update circuit is configured to receive, from the first memory, parent path values, and provide, to a second memory, child path values based on the parent path values. The sort circuit is configured to receive, from the second memory, the child path values; and provide, to the first memory, surviving child path values based on the child path values.