Polar Sequence Mapping for Multi-Length 5G Rate Matching

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Solution Overview

Problem

Current solutions lack an effective sequence determination scheme for 5G New Radio Access Technology (RAT), particularly in handling different mother code lengths for Polar codes, which complicates hardware implementation and reduces efficiency due to the need for distinct hardware configurations for permutation and rate matching of bits.

Innovation Solution

A method and apparatus that map a first bit sequence to a specified position based on M_index to obtain a Polar encoded bit sequence, allowing for the selection of T bits as the bit sequence to be transmitted, utilizing transforms such as row or column permutations to reuse hardware across varying mother code lengths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different hardware implementations are used for different mother code lengths, then the Polar code encoding and rate matching can be performed accurately, but the device complexity increases and hardware resources are wasted

Engineering Contradiction:
ImprovePolar code encoding accuracyVSAvoidhardware implementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a single hardware implementation that can handle multiple mother code lengths (N=128, 256, 512, 1024) through configurable parameters. The same hardware structure performs Polar code encoding and rate matching for different code lengths by adjusting the mother code length parameter, eliminating the need for separate hardware implementations for each code length while maintaining encoding accuracy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate hardware is allocated for each mother code length, then the encoding performance is optimized for specific lengths, but the resource utilization decreases and cost increases

Engineering Contradiction:
Improvedecoding performanceVSAvoidhardware resource utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements a universal hardware architecture that can be configured to support multiple mother code lengths (N=128, 256, 512, 1024) and various information bit lengths (K). This single hardware system replaces what would otherwise require multiple dedicated hardware implementations, thereby improving resource utilization and reducing costs while maintaining optimized decoding performance across different code lengths through proper configuration of the mother code length parameter.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If conventional permutation and rate matching methods are used for different code lengths, then the bit placement optimization is achieved, but the hardware reconfiguration requirement increases system complexity

Engineering Contradiction:
ImproveBlock Error Rate reductionVSAvoidhardware reconfiguration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by introducing a configurable mother code length parameter that allows the same hardware implementation to adapt to different code lengths (N=128, 256, 512, 1024). By changing this parameter, the hardware automatically performs the appropriate permutation and rate matching operations for the selected code length, achieving bit placement optimization without requiring physical reconfiguration of the hardware structure.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11271592B2Method and apparatus for sequence determination, device and storage medium
Publication Date: 2022.03.08 ZTE CORP
  • US11271592B2 patent drawing
  • US11271592B2 patent drawing

AI summary

The present disclosure provides a method and an apparatus for sequence determination, a device and a storage medium. The method for sequence determination includes: mapping a first bit sequence having a length of K bits to a specified position based on M_index to obtain a second bit sequence; applying Polar encoding to the second bit sequence to obtain a Polar encoded bit sequence; and selecting T bits based on the Polar encoded bit sequence as a bit sequence to be transmitted, where K and T are both non-negative integers and K≤T.