Polar Transmitter Clock Correction for AM-FM Delay Alignment

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Solution Overview

Problem

Low-power RF transceivers using a two-point-PLL modulator concept face signal quality degradation due to static delay mismatch and FM-to-AM distortion when amplitude modulation is combined with frequency or phase modulation, particularly in Bluetooth EDR 2Mbps and 3Mbps, leading to degraded RF performance and potential failure to meet Bluetooth standards.

Innovation Solution

A circuit for a polar transmitter that includes a frequency modulation path, a non-uniform clock time error calculation unit to determine a delay value based on the frequency modulation signal, and a non-uniform clock correction unit to generate a modified amplitude modulation signal, thereby preventing signal quality degradation by aligning the AM and FM paths with a variable time delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the AM path is clocked with the LO signal generated by the FM path, then the hardware structure is simplified, but FM-to-AM distortion arises and variable time delay occurs causing signal quality degradation

Engineering Contradiction:
Improvehardware structureVSAvoidsignal quality
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces a delay correction unit as an intermediary component between the FM path and AM path. This unit receives the LO signal and generates a corrected clock signal with adjusted delay timing, which then clocks the AM path. The delay correction unit acts as a mediator that eliminates the harmful variable time delay while maintaining the simplified hardware structure of using the LO signal for clocking.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent dynamically adjusts the delay parameter of the clock signal used to clock the AM path. The delay correction unit modifies the timing parameter of the LO signal based on the instantaneous frequency deviation, creating a corrected clock signal with optimized delay characteristics. This parameter adjustment eliminates FM-to-AM distortion while preserving the low-complexity hardware architecture.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If static delay equalization is used to correct delay mismatch, then the hardware structure remains simple, but RF performance is degraded due to inability to compensate for variable time delay

Engineering Contradiction:
Improvehardware structureVSAvoidRF performance
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent transitions from static delay equalization to dynamic delay correction. The delay correction unit continuously adjusts the delay timing of the clock signal based on real-time frequency modulation conditions. This dynamic adjustment mechanism enables compensation for variable time delay while maintaining relatively simple hardware, thereby improving RF performance metrics such as in-band emissions and D-EVM.

Inventive Principle:
Principle #15Dynamics

3Use of energy by moving object

If a low-power two-point-PLL modulator concept is used, then current consumption is reduced, but signal quality degradation occurs when amplitude modulation is combined with frequency or phase modulation

Engineering Contradiction:
Improvecurrent consumptionVSAvoidsignal quality
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The delay correction unit serves as an intermediary that enables the low-power two-point-PLL modulator to achieve high signal quality. By inserting this correction stage, the system maintains the energy efficiency of the two-point-PLL architecture while eliminating FM-to-AM distortion and variable time delay effects, thus achieving both low current consumption and high signal quality required for Bluetooth EDR standards.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4340218A1Circuit for polar transmitter and method of operating a polar transmitter
Publication Date: 2024.03.20 NXP BV
  • EP4340218A1 patent drawingFigure 1~3
  • EP4340218A1 patent drawingFigure 4~6
  • EP4340218A1 patent drawingFigure 7~8

AI summary

There is described a circuit (101, 201, 501) for a polar transmitter, the circuit comprising a frequency modulation path (110, 210, 510) coupled to receive a frequency modulation signal (FM(nT)) and configured to generate a frequency modulated signal (LO(t)) based on the frequency modulation signal; a non-uniform clock time error calculation unit (120, 220, 320, 520) configured to determine a delay value (delay(nT)) based on the frequency modulation signal; an amplitude modulation path (130, 230, 530) coupled to receive an amplitude modulation signal (AM(nT)) and comprising a non-uniform clock correction unit (134, 234, 434, 536) coupled to the non-uniform clock time error calculation unit and configured to generate a modified amplitude modulation signal (AM _mod(nT), AM src_mod(nT)) based on the amplitude modulation signal and the delay value; and a transmitter (140, 241) coupled to the frequency modulation path and the amplitude modulation path, wherein the transmitter is configured to generate a modulated signal based on the frequency modulated signal and the modified amplitude modulation signal. Furthermore, a method of operating a polar transmitter is described.