Digital Polar Transmitter Delay Alignment Across Multiple Clock Domains
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Solution Overview
Problem
Modern wireless communication standards such as GSM, EDGE, WCDMA, and WiMAX require precise alignment between amplitude and phase/frequency modulation paths in digital polar transmitters to maintain stringent performance criteria, which is challenging due to coarser clock domains and digitally controlled analog components, leading to potential signal distortion if not accurately aligned.
Innovation Solution
A fully digital delay alignment mechanism using programmable delay elements across multiple clock domains, tapped delay lines, and signal correlation techniques to achieve sub-nanosecond alignment, accounting for processing delays and compensating for analog propagation delays, ensuring precise timing alignment between amplitude and phase/frequency modulation paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If coarser clock domains are used for power efficiency, then energy consumption is reduced, but timing alignment precision between AM and PM paths deteriorates
Solution Approach 1:
The patent divides the delay alignment mechanism into multiple clock domains (coarse and fine adjustment domains) and segments the delay elements across different operational rates. This allows the system to use lower clock rates for most operations (saving power) while maintaining sub-nanosecond alignment precision through the segmented delay structure.
Solution Approach 2:
The patent implements dynamic delay adjustment where delay elements can be programmatically configured based on operating conditions. The system dynamically switches between different clock domains and adjusts delay values to maintain precision across varying power states and operational modes.
2Measurement precision
If programmable delay elements are added to achieve precise alignment, then timing alignment precision is improved, but device complexity increases
Solution Approach 1:
The patent designs delay elements that serve multiple functions: they provide both coarse and fine delay adjustment, operate across multiple clock domains, and can be programmed for different alignment scenarios. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby managing complexity while achieving precision.
Solution Approach 2:
The patent achieves precise delay alignment by programmatically changing delay parameters rather than using fixed complex circuitry. The delay values are adjustable through digital control, allowing the same hardware structure to adapt to different timing requirements without increasing physical complexity.
3Adaptability or versatility
If multiple clock domains are used for delay alignment, then timing flexibility is improved, but synchronization difficulty increases
Solution Approach 1:
The patent introduces intermediary synchronization mechanisms that mediate between multiple clock domains. These intermediaries coordinate the different clock rates and ensure proper phase relationships, making the synchronization of multiple clock domains manageable while maintaining timing flexibility.
Data Source
AI summary
A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.