Polar Transformation Circuit Using Iterative XOR and Bit Interleaving
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Solution Overview
Problem
Existing methods for computing the polar transformation of a sequence of 2n bits are either slow and resource-intensive when performed on a CPU or DSP, or require a large number of logic gates when implemented using dedicated digital hardware logic.
Innovation Solution
An electronic apparatus configured to store an input sequence of 2n bits and perform a sequence of bitwise XOR operations and bit-interleave operations n times, where each iteration updates the working bit sequence, ultimately producing the polar transformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CPU or DSP is used to perform matrix multiplication for polar transformation, then processing flexibility is maintained, but processing speed is slow and memory resources are significantly consumed
Solution Approach 1:
The patent replaces the general-purpose CPU/DSP matrix multiplication approach with a dedicated hardware logic circuit implementation. The mechanical/computational system (CPU executing software algorithms) is substituted with an electronic hardware system (custom logic circuit), achieving faster processing speed while maintaining the polar transformation functionality required for 5G NR.
2Productivity
If dedicated digital hardware logic with n stages of XOR gates is used, then processing speed is improved, but the number of logic gates required becomes very large
Solution Approach 1:
The patent segments the polar transformation computation into n iterative stages, where each stage processes a portion of the bit sequence. Instead of implementing all 2^n - 1 XOR gates simultaneously, the computation is divided into sequential steps that process the input bits through multiple passes, reducing the instantaneous hardware complexity while maintaining the transformation accuracy.
Solution Approach 2:
The patent employs periodic action by repeating the same XOR and interleaving operations n times in an iterative manner. The hardware circuit performs the same set of operations cyclically across different bit positions and stages, allowing reuse of the same logic gates across multiple iterations rather than requiring dedicated gates for each transformation path.
3Manufacturing precision
If a network of 2n-1 XOR gates per stage is implemented, then polar transformation accuracy is achieved, but hardware area occupation increases significantly
Solution Approach 1:
The patent makes the XOR gates and interleaving logic universal by designing them to perform multiple functions across different stages and bit positions. The same hardware components are reused iteratively to process different portions of the bit sequence, allowing a single set of logic gates to accomplish what would otherwise require many dedicated gates, thereby reducing overall hardware area while maintaining transformation accuracy.
Data Source
AI summary
A radio apparatus is configured to implement a method for computing a polar transformation of an input bit sequence of 2n bits for transmission by radio. The method comprises storing the input bit sequence in electronic memory as a working bit sequence, and then computing a bitwise XOR of a contiguous first half of the working bit sequence with a contiguous second half of the working bit sequence, the second half being disjoint from the first half. The result of the bitwise XOR is stored in electronic memory. A bit-interleave sequence is generated by interleaving the result of the bitwise XOR with the second half of the working bit sequence. Next, the bit interleave sequence is stored as the updated working bit sequence. After n iterations of the previous steps are performed, the working bit sequence, or a contiguous subsequence thereof, is the polar transformation of the input sequence.