Polarization Gate Stack SRAM Read Disturb Mitigation
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Solution Overview
Problem
As transistor sizes in SRAM memory cells decrease, variations in transistor operating characteristics increase, leading to reduced operating margins and a higher likelihood of read disturb during operations.
Innovation Solution
Incorporating a polarization layer, such as ferroelectric materials or nanocrystals, in the gate stack of transistors to reduce leakage current and enhance read current by controlling the gate bias and threshold voltage, thereby reducing the likelihood of read disturb and improving read operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor sizes are reduced to decrease memory cell size, then area is reduced, but transistor operating characteristics vary more and operating margins decrease
Solution Approach 1:
The patent introduces a polarization layer in the gate stack that changes the electrical parameters of the transistor by providing an additional gate voltage component. This polarization layer can be toggled between polarized and depolarized states to dynamically adjust the threshold voltage and operating characteristics of the transistor, thereby maintaining reliable operation even as transistor dimensions are reduced.
Solution Approach 2:
The gate stack is constructed as a composite structure including multiple layers: gate electrode, gate dielectric, and polarization layer (ferroelectric material or nanocrystals). This composite material structure combines the electrical insulation properties of the gate dielectric with the polarization switching properties of the ferroelectric layer, enabling dynamic control of transistor characteristics to compensate for variability in scaled devices.
2Area of moving object
If transistor sizes are reduced to decrease memory cell size, then area is reduced, but read disturb increases
Solution Approach 1:
The polarization layer provides dynamic parameter adjustment by switching between polarized and depolarized states. During read operations, the polarized state enhances the gate voltage to ensure strong transistor conduction, reducing the likelihood of read disturb. This dynamic parameter change compensates for the increased sensitivity to read disturbances in scaled transistors.
Solution Approach 2:
The polarization layer is pre-polarized before read operations to establish a strong gate voltage component that ensures reliable transistor conduction during subsequent read operations. This preliminary action of polarizing the layer before the actual read operation prevents read disturb by ensuring the transistor remains firmly in the on-state during bit line sensing.
3Loss of energy
If polarization layer is added to gate stack to reduce leakage current, then leakage current decreases, but device complexity increases
Solution Approach 1:
The gate stack is constructed as a composite structure including multiple layers: gate electrode, gate dielectric, and polarization layer (ferroelectric material or nanocrystals). This composite material structure combines the electrical insulation properties of the gate dielectric with the polarization switching properties of the ferroelectric layer, enabling dynamic control of transistor characteristics to compensate for variability in scaled devices.
Solution Approach 2:
The patent introduces a polarization layer in the gate stack that changes the electrical parameters of the transistor by providing an additional gate voltage component. This polarization layer can be toggled between polarized and depolarized states to dynamically adjust the threshold voltage and operating characteristics of the transistor, thereby maintaining reliable operation even as transistor dimensions are reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The polarization layer effectively decreases leakage current when transistors are turned off and increases read current during operations, reducing the risk of read disturb and enhancing the speed of read operations while maintaining data integrity.
Implementation Method 1
A gate stack of one transistor of each inverter includes a polarization layer. The polarization layer may include a ferroelectric material and/or nanocrystals.
Implementation Method 2
Polarization of the polarization layer is configured to enhance the gate bias during read operations and to thus increase a drive current of the associated transistors.
Data Source
AI summary
One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.