Multi-Stage Packet Classification Using Policy Vectors
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Solution Overview
Problem
Existing packet classification schemes in multi-stage switches face challenges with high power consumption, chip area requirements, and memory bandwidth limitations, making them impractical for high-speed switches and routers, particularly in complex routing systems like data centers.
Innovation Solution
A method is introduced that produces policy vectors based on portions of a data packet, combining them to trigger processing at the multi-stage switch, using hardware implementation for efficient processing and storage, with compression and decompression techniques to reduce memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Ternary Content Addressed Memories (TCAMs) or software algorithms are used for packet classification, then classification functionality is achieved, but power consumption and chip area requirements become undesirable
Solution Approach 1:
The packet classification function is divided into multiple stages, with each stage processing a portion of the classification task. This segmentation allows the system to achieve comprehensive classification functionality while using smaller, more power-efficient hardware components at each stage rather than requiring a large TCAM or complex software algorithm in a single stage.
Solution Approach 2:
The patent replaces traditional TCAM-based classification mechanisms with a multi-stage classification apparatus that uses simpler comparison logic and policy vectors. This substitution reduces the power consumption and chip area requirements while maintaining classification effectiveness.
2Ease of manufacture
If external memory data structures are used in software packet classification algorithms, then classification is achieved, but memory bandwidth limitations prevent use in very high speed switches and routers
Solution Approach 1:
The patent combines the classification logic and policy data into an integrated multi-stage classification apparatus implemented in hardware. This merging eliminates the need for external memory accesses, allowing the system to achieve high-speed processing by keeping all classification data and logic within the switch fabric.
Solution Approach 2:
The system pre-processes packet information at multiple stages before final classification, extracting and comparing relevant fields in advance. This preliminary action at each stage reduces the complexity of subsequent classification steps and enables high-speed processing without external memory bandwidth constraints.
3Ease of manufacture
If known packet classification schemes are implemented, then classification is achieved, but power consumption requirements and inefficient chip designs prevent scaling for complex routing systems
Solution Approach 1:
The multi-stage classification apparatus is designed with dynamic policy vectors that can be updated and reconfigured without requiring complete system redesign. This dynamic architecture allows the classification system to scale to complex routing systems by adapting to different classification requirements while maintaining power efficiency and chip area optimization.
Data Source
AI summary
In one embodiment, a method, comprising producing a first policy vector based on a first portion of a data packet received at a multi-stage switch. The method also includes producing a second policy vector based on a second portion of the data packet different than the first portion of the data packet. A third policy vector is produced based on a combination of at least the first policy vector and at least the second policy vector. The third policy vector including a combination of bit values configured to trigger an element at the multi-stage switch to process the data packet.