Polish Stop and Sealing Layer for Deep Trench Isolation
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Solution Overview
Problem
Deep trench isolation in semiconductor devices faces challenges with the use of low-cost dielectric films, which have less desirable electrical characteristics, and high-quality films are unsuitable for filling due to high costs, leading to issues like polysilicon stringers and electrical shorts.
Innovation Solution
A method that eliminates vertical steps by using a lower-quality silicon dioxide for deep trench filling and a higher-quality oxide in the active region, with a silicon nitride layer preventing gaps and ensuring continuous planarization, allowing for reduced fabrication costs without compromising electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If low-cost dielectric films are used to fill deep trenches, then manufacturing cost is reduced, but electrical characteristics deteriorate and vertical steps form causing polysilicon stringers
Solution Approach 1:
The patent applies local quality by using different dielectric materials in different regions: low-cost dielectric material fills the deep trench isolation region, while high-quality dielectric material is used in the shallow trench isolation region and cap layer. This regional differentiation allows cost reduction in non-critical areas while maintaining electrical performance in active device regions, preventing polysilicon stringers where they would cause failures.
2Reliability
If high-quality dielectric films are used to fill deep trenches, then electrical characteristics are improved, but manufacturing cost increases
Solution Approach 1:
The patent implements local quality by strategically placing high-quality dielectric material only where electrical performance is critical (shallow trench isolation and cap layers over active regions), while using low-cost dielectric material for deep trench filling where electrical characteristics are less demanding. This optimized material distribution maintains device reliability while significantly reducing manufacturing costs.
3Ease of manufacture
If both low-quality and high-quality films are exposed at the surface, then cost is reduced, but vertical steps appear causing polysilicon stringers and electrical shorts
Solution Approach 1:
The patent solves the surface flatness problem by introducing a planarization layer (CMP or spin-on-glass) that covers the topography variations caused by differential etching of low-quality and high-quality dielectric films. This additional dimensional layer eliminates vertical steps and gaps, preventing polysilicon stringer formation during subsequent deposition while maintaining the cost benefits of using mixed dielectric materials.
4Area of stationary object
If polysilicon film thickness is increased to cover steps, then surface coverage is improved, but polysilicon stringers form due to excessive thickness at step locations
Solution Approach 1:
The patent applies preliminary action by performing planarization (CMP or spin-on-glass deposition) before polysilicon deposition to eliminate surface steps and gaps. This pre-treatment creates a flat surface that ensures uniform polysilicon film thickness, preventing stringer formation while maintaining complete surface coverage. The planarization step prepares the surface in advance, allowing subsequent polysilicon deposition to be uniform without requiring excessive thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the formation of polysilicon stringers and electrical shorts, maintaining device performance while lowering costs by using lower-quality dielectric materials effectively.
Implementation Method 1
A second silicon nitride layer is then deposited over the planarized second silicon dioxide layer. The second silicon nitride layer and the second silicon dioxide layer are etched, exposing a region substantially circumscribed laterally by the shallow trench and a deep trench is etched in the exposed region.
Implementation Method 2
Exposed sidewalls and a bottom region of the shallow trench are then oxidized, forming a liner oxide.
Data Source
AI summary
A method and resulting device that eliminates vertical steps or gaps in a deep trench isolation region and, thus, eliminates or drastically reduces a possibility of polysilicon stringers. Additionally, the invention allows an inexpensive dielectric material, for example a lower-quality silicon dioxide to be used to fill the deep trench and a higher quality oxide, in an electrically active region, to be used on an uppermost portion of the deep trench without affecting device performance or increasing a possibility of forming polysilicon stringers.