Double-Side Polishing Pad Thickness Optimization
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Solution Overview
Problem
In semiconductor wafer double-side polishing, there is a trade-off between achieving a negative F-ZDD (Front Z-Height Double Differentiation) and controlling GBIR (Global BackSurface-Referenced Ideal Plane/Range) to a small value, as increasing polishing pad thickness to achieve F-ZDD < 0 results in an increased GBIR, making it difficult to satisfy both requirements simultaneously.
Innovation Solution
A double-side polishing method and apparatus where the thickness of polishing pads on upper and lower turn tables satisfy specific conditions (1.0 ≤ A+B ≤ 2.0 and A/B > 1.0), optimizing the ratio and sum of pad thicknesses to control F-ZDD to a negative value while keeping GBIR small, with preferred conditions of 1.5 ≤ A/B ≤ 2.5 and Shore A hardness of 85 or more for accurate control and preventing pad tearing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thickness of polishing pads is increased to control F-ZDD to a negative value, then the F-ZDD is controlled, but the polishing pad may tear during double-side polishing
Solution Approach 1:
The patent resolves this contradiction by optimizing the thickness parameters of the polishing pads. By setting the upper polishing pad thickness to 0.5-2.0 mm and the lower polishing pad thickness to 0.1-1.0 mm, the pads are thick enough to achieve F-ZDD < 0 but not so thick as to cause tearing during operation. This parameter optimization balances structural integrity with flatness control requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method and apparatus enable the simultaneous achievement of F-ZDD < 0 and GBIR ≤ required value, ensuring the semiconductor wafer's flatness meets customer specifications by optimizing polishing pad thickness ratios and Shore A hardness, preventing excessive GBIR and pad tearing.
Implementation Method 1
the semiconductor wafer is subjected to sliding motion to polish the both surfaces of the front surface and the back surface simultaneously
Data Source
AI summary
A double-side polishing method, including: simultaneously polishing both surfaces of a semiconductor wafer by holding the semiconductor wafer in a carrier, interposing the held semiconductor wafer between an upper turn table and a lower turn table each having a polishing pad attached thereto, and bringing both surfaces of the semiconductor wafer into sliding contact with the polishing pads, wherein the semiconductor wafer is polished under a condition that a thickness A (mm) of the polishing pad attached to the upper turn table and a thickness B (mm) of the polishing pad attached to the lower turn table satisfy relations of 1.0≤A+B≤2.0 and A/B>1.0. This provides a double-side polishing method capable of obtaining a semiconductor wafer in which F-ZDD<0 while controlling the GBIR value to be equal to or smaller than a required value.