Asynchronous Data Transfer via Poll Signal Inversion

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Solution Overview

Problem

Existing data transfer systems face challenges in transferring continuous data between circuits operating on asynchronously different clock signals, as they require synchronization and handshake mechanisms that can be complex and inefficient.

Innovation Solution

A data transfer system comprising a transmission circuit operating on a first clock signal and a receiving circuit on a second clock signal, where the transmission circuit outputs a poll signal with inverted levels, and the receiving circuit generates synchronous poll signals and selects reception data based on these signals, allowing asynchronous data transfer without mutual handshake.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If handshake mechanisms are used for data transfer between circuits with different clock signals, then data transfer reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoidsynchronization mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the essential synchronization information (poll signal) from the complex handshake mechanism and transmits it separately through a dedicated poll signal line. This separates the critical timing information from the data transmission path, allowing the receiving circuit to synchronize data reception without requiring complex bidirectional handshake protocols between circuits operating on different clock domains.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The poll signal acts as an intermediary that carries timing information from the transmitting circuit to the receiving circuit. Instead of direct handshake between the two circuits, the poll signal mediates the synchronization process by providing the receiving circuit with the timing reference needed to sample data at the correct moments, thereby simplifying the overall synchronization mechanism.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If multiple reception timings are used to generate synchronous poll signals, then data selection accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvedata selection accuracyVSAvoidsignal generating circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the data reception process into multiple discrete timing instances, where the receiving circuit samples the poll signal at several different timings (first, second, and third reception timings). This segmentation allows the circuit to compare poll signal values across different time points and select the data corresponding to the most reliable sampling moment, thereby improving data selection accuracy through temporal diversification.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs excessive action by sampling the poll signal more times than strictly necessary (at multiple reception timings rather than a single timing). This redundant sampling provides multiple opportunities to capture the correct poll signal value, and through comparison of these multiple samples, the circuit can identify and select the most accurate data, compensating for potential timing mismatches or signal instability.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8774292B2Data transfer system, data transfer method, receiving circuit, and receiving method
Publication Date: 2014.07.08 SOCIONEXT INC
  • US8774292B2 patent drawing
  • US8774292B2 patent drawing
  • US8774292B2 patent drawing

AI summary

A data transfer system includes a transmission circuit, which operates by a first clock signal, and a receiving circuit, which operates by a second clock signal different from the first clock signal. The transmission circuit includes an output circuit that outputs a poll signal, of which a level is logically inverted in accordance with a transmission timing of transmission data from the transmission circuit to the receiving circuit. A first signal generating circuit receives the transmission data at a plurality of timings and generates plural sets of reception data corresponding to the plurality of timings. A second signal generating circuit receives the poll signal at the plurality of timings and generates synchronous poll signals corresponding to the plurality of timings. A data selecting circuit compares levels of the synchronous poll signals with each other and selects one of the sets of reception data based on the comparison result.