Polling-Based Storage Command Processing for CPU Utilization
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Solution Overview
Problem
In Fibre Channel configurations, the rigid allocation of CPU cores for interrupt processing leads to inefficient CPU utilization due to unmanaged competition between polling operations and interrupts, resulting in decreased efficiency in processing storage commands.
Innovation Solution
Assigning a first set of interrupts for exclusive processing by a first set of CPU cores and converting a second set of interrupts to polling operations, which are then processed using a second set of CPU cores, allowing for more flexible CPU core allocation and increased efficiency in processing storage commands without increasing IO latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interrupts are used for processing storage commands, then processing speed is improved, but CPU utilization efficiency deteriorates due to unmanaged competition between polling operations and interrupts
Solution Approach 1:
The patent segments interrupt handling into two distinct paths: a first interrupt handler for high-priority IO command interrupts that maintains traditional interrupt processing, and a second interrupt handler for lower-priority interrupts that are converted to polling operations. This segmentation allows critical storage commands to be processed immediately via interrupts while non-critical commands use polling, resolving the contradiction between speed and CPU efficiency.
Solution Approach 2:
Different quality of service is applied to different interrupt types based on their priority. High-priority IO command interrupts receive immediate attention through traditional interrupt mechanisms, while lower-priority interrupts are handled through polling. This local differentiation optimizes CPU utilization by matching the processing mechanism to the urgency of each command type.
2Productivity
If more CPU cores are assigned to storage application, then storage processing capacity is improved, but Fibre Channel interrupt processing capability deteriorates
Solution Approach 1:
The patent introduces dynamic interrupt handling where the processing mechanism adapts based on interrupt priority and system state. The second interrupt handler dynamically converts certain interrupts to polling operations, allowing flexible allocation of CPU resources between storage application and Fibre Channel processing without rigid core assignment, thus maintaining both storage capacity and interrupt processing capability.
Solution Approach 2:
The patent changes the processing parameter from traditional interrupt handling to polling for specific interrupt types. By converting lower-priority interrupts to polling operations, the system can allocate more CPU cores to storage application while maintaining Fibre Channel processing capability through the hybrid approach of interrupt + polling.
3Ease of operation
If rigid allocation of CPU cores is used between storage application and Fibre Channel interrupts, then resource management is simplified, but CPU utilization efficiency deteriorates
Solution Approach 1:
The patent segments the interrupt handling logic into two distinct handlers with clear responsibility boundaries. The first handler manages high-priority IO commands with traditional interrupts, while the second handler manages lower-priority interrupts through polling conversion. This segmentation maintains operational simplicity while dramatically improving CPU utilization efficiency through the hybrid processing approach.
Data Source
AI summary
A method, computer program product, and computing system for assigning a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores. A second set of interrupts may be assigned for processing by a second set of CPU cores. The first set of interrupts may be processed using the first set of CPU cores. The second set of interrupts may be converted to a set of polling operations, thus defining a set of converted polling operations. The set of converted polling operations may be processed using the second set of CPU cores.