Poly Cut Layout for PMOS-NMOS Threshold Voltage Matching
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, particularly in managing the poly extension effect, which affects the threshold voltage of transistors and overall circuit performance, as existing methods struggle to optimize the positioning of poly cut patterns to balance the poly extension effects of PMOS and NMOS transistors.
Innovation Solution
The method involves generating layout designs that determine the difference in poly extension effects between PMOS and NMOS transistors, adjusting the positioning of poly cut patterns to optimize transistor performance, and fabricating the integrated circuit accordingly, ensuring that the poly extension effect of PMOS transistors is either equal to, greater than, or less than that of NMOS transistors based on specific conditions to enhance circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the poly cut pattern is positioned to reduce poly extension effect, then transistor threshold voltage control is improved, but circuit performance optimization becomes more difficult due to conflicting requirements between PMOS and NMOS transistors
Solution Approach 1:
The patent applies local quality by differentiating the poly cut pattern positioning for PMOS and NMOS transistors. Specifically, the poly cut pattern is positioned at different locations relative to PMOS and NMOS transistors to compensate for their different poly extension effects. For PMOS transistors, the poly cut pattern is positioned to achieve a first poly extension length, while for NMOS transistors, it is positioned to achieve a second poly extension length, thereby optimizing threshold voltage control for each transistor type locally
Solution Approach 2:
The patent employs asymmetry by intentionally creating asymmetric poly extension lengths for PMOS and NMOS transistors. The poly cut pattern is deliberately positioned to create different poly extension effects for the two transistor types, with the first poly extension length for PMOS being different from the second poly extension length for NMOS. This asymmetric approach allows independent optimization of threshold voltages for both transistor types despite using a common poly cut pattern design
2Reliability
If the poly extension length is increased to adjust threshold voltage, then transistor performance is improved, but the poly extension effect difference between PMOS and NMOS transistors creates manufacturing complexity
Solution Approach 1:
The patent applies local quality by differentiating the poly cut pattern positioning for PMOS and NMOS transistors. Specifically, the poly cut pattern is positioned at different locations relative to PMOS and NMOS transistors to compensate for their different poly extension effects. For PMOS transistors, the poly cut pattern is positioned to achieve a first poly extension length, while for NMOS transistors, it is positioned to achieve a second poly extension length, thereby optimizing threshold voltage control for each transistor type locally
Solution Approach 2:
The patent employs feedback by using the determined difference in poly extension effects between PMOS and NMOS transistors to guide the positioning of the poly cut pattern. The system first determines the poly extension effect difference, then uses this information to position the poly cut pattern accordingly, creating a feedback loop that optimizes threshold voltage control based on actual transistor characteristics
Data Source
AI summary
A method of fabricating an integrated circuit. The method includes generating two first-type active zones and two second-type active zones, and generating a gate-strip intersecting the two first-type active zones and the two second-type active zones. The method further includes patterning one or more poly cuts intersecting the gate-strip based on a determination of a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.