Poly Silicon Fuse Structure for Low-Voltage Memory Trimming
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Solution Overview
Problem
As the integration level of memory devices increases, the fabrication process becomes more complicated, and the process window narrows, making it challenging to effectively utilize fuse elements for manufacturing yield improvement and customization.
Innovation Solution
A semiconductor device with a fuse component is designed, featuring a poly silicon portion with a bottom tip pointing to the substrate, a dielectric film with a V-shape cross-section, and a conductive portion on the poly silicon portion. This configuration induces a corona discharge at the bottom tip when an external voltage is applied, reducing the breakdown voltage required to blow the fuse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional fuse structure is used in high integration memory devices, then the manufacturing yield can be improved through defect replacement, but the breakdown voltage remains too high requiring excessive electrical current that may damage surrounding circuits
Solution Approach 1:
The patent changes the geometric parameters of the fuse structure by introducing a tip at the bottom end of the poly silicon portion. This geometric parameter change concentrates the electrical field at the tip, which reduces the breakdown voltage and consequently reduces the electrical current required to blow the fuse while maintaining its yield improvement function
Solution Approach 2:
The patent extends the fuse structure into the substrate by creating a tip that protrudes into the substrate, adding a vertical dimension to the fuse structure. This three-dimensional configuration creates field concentration at the tip, reducing the current requirement compared to conventional planar fuse structures
2Ease of operation
If high electrical current is used to blow the fuse, then the fuse can be disconnected, but the surrounding circuits may be damaged due to the excessive current
Solution Approach 1:
By changing the geometric parameters to include a sharp tip at the bottom end of the poly silicon portion, the electrical field is concentrated at the tip, which reduces the breakdown voltage to a safe level that allows fuse disconnection without damaging surrounding circuits
3Reliability
If the fuse structure is extended into the substrate, then the electrical field is concentrated and breakdown voltage is reduced, but the fabrication process becomes more complicated
Solution Approach 1:
The patent performs preliminary actions during the fabrication process by forming the tip structure early in the process flow, before subsequent processing steps. The tip is formed during the poly silicon deposition and patterning stages, and subsequent steps are designed to accommodate this pre-formed structure, thereby managing fabrication complexity
Solution Approach 2:
The poly silicon portion serves multiple functions: it acts as the fuse element, provides structural support, and its tip configuration creates field concentration. This multi-functionality reduces the need for additional specialized components or processes, helping to manage fabrication complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design allows for a reduced breakdown voltage, making it easier to disconnect or blow the fuse component, thereby improving manufacturing yield and enabling custom applications with reduced electrical current requirements.
Implementation Method 1
This configuration induces a corona discharge at the bottom tip when an external voltage is applied, reducing the breakdown voltage required to blow the fuse
Implementation Method 2
etching the portion of the substrate includes using NaOH as etchant
Data Source
AI summary
A semiconductor device includes a substrate, a plurality of gate structures, and a fuse component. The substrate has an active region and a peripheral region surrounding the active region. The gate structures are disposed in the active region of the substrate. The fuse component is disposed at the peripheral region of the substrate. The fuse component has a poly silicon portion having a bottom tip pointing to the substrate, a dielectric film between the substrate and the poly silicon portion, and a conductive portion on the poly silicon portion. A method of forming a semiconductor device is also disclosed.