Poly Gate Structure with Asymmetric Source Drain Widths
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Solution Overview
Problem
The formation of divots in shallow trench isolation (STI) structures during the fabrication of integrated chips leads to performance degradation of transistor devices due to enhanced electric fields, causing early turning on of transistors and non-uniform signal amplification.
Innovation Solution
A transistor device with a gate structure comprising multiple poly gate electrode regions having different types of dopants, where the source and drain regions have smaller widths than the channel region, separating the effective channel region from the edges of the isolation structure, and using different dopant types to tune the threshold voltage and offset the effects of divots and dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If divots are formed in shallow trench isolation structures during fabrication, then manufacturing process is simplified, but transistor performance degrades due to enhanced electric fields causing early turning on and non-uniform signal amplification
Solution Approach 1:
The patent applies local quality by creating asymmetric source and drain region widths to specifically address the divot problem at isolation structure edges. The narrower source/drain regions are positioned away from divots while the channel region maintains full width, providing localized compensation for electric field enhancement only where needed rather than redesigning the entire transistor structure
Solution Approach 2:
The patent changes the width parameter of source and drain regions relative to the channel region. By making source/drain widths smaller than channel width, the effective channel length increases near divots, compensating for the enhanced electric field effect and maintaining uniform transistor characteristics across the device
2Reliability
If source and drain regions have smaller widths than channel region, then divot effects are mitigated and transistor performance improves, but device complexity increases
Solution Approach 1:
The patent segments the transistor structure into distinct width zones: narrower source/drain regions and a wider channel region. This segmentation allows each region to serve its specific function - source/drain regions are optimized for connection while the channel region maintains full width for current flow, with the width transition providing automatic compensation for divot effects without additional process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the impact of divots on the electric field, improving transistor performance by mitigating the double hump effect in drain current and ensuring uniform signal amplification, while allowing for low-cost fabrication compatible with standard processes without compromising reliability.
Implementation Method 1
using different dopant types to tune the threshold voltage and offset the effects of divots and dopant diffusion
Data Source
AI summary
An integrated chip includes a substrate, an isolation structure and a poly gate structure. The isolation structure includes dielectric materials within the substrate and having sidewalls defining an active region. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source region has a first width along a second direction perpendicular to the first direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and larger than the first and second widths. The poly gate structure extends over the channel region. The poly gate structure includes a first doped region having a first type of dopants and a second doped region having a second type of dopants. The second type is different from the first type.