Poly Gate Groove Structure to Reduce CMP Dishing
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Solution Overview
Problem
Current semiconductor structures face performance issues due to top surface dishing problems during the planarization process, particularly in high voltage and medium voltage devices, where the poly gate layer's thickness is reduced, leading to operational inefficiencies.
Innovation Solution
A semiconductor structure is developed with a poly gate layer featuring a bottom and top gate layer configuration that includes a groove, along with a polish block layer on the sidewall, which helps in alleviating top surface dishing by controlling the line width, top surface area, and spacing, thereby improving the poly gate layer's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional poly gate layer structure is used in high voltage devices, then the device can operate at high voltages, but top surface dishing occurs during planarization process reducing gate layer thickness and performance
Solution Approach 1:
The poly gate layer is segmented into multiple thickness regions: a first region with greater thickness and a second region with lesser thickness. This segmentation allows different portions of the gate layer to serve different functional requirements, with the thicker first region providing structural support to prevent dishing while the thinner second region provides the active gating function.
Solution Approach 2:
Different regions of the poly gate layer are given different local qualities in terms of thickness. The first region has greater thickness specifically positioned to address the dishing problem during planarization, while the second region has lesser thickness optimized for device operation. This local differentiation resolves the contradiction between structural integrity and functional performance.
2Manufacturing precision
If the poly gate layer top surface area is reduced to alleviate dishing, then planarization improves, but the gate control capability may be affected
Solution Approach 1:
The solution moves from controlling only the top surface area to controlling the vertical dimension by creating a thickness gradient. The poly gate layer transitions from a uniform thin layer to a structured layer with varying thickness, adding a vertical dimension to the design. This allows the top surface to remain compact for good planarization while the underlying thicker region maintains structural support and gate control capability.
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The forming method includes: forming discrete poly gate layers on a base of a first region and a second region, the poly gate layer of the first region including a bottom gate layer and a top gate layer protruding out of the bottom gate layer, the top gate layer and the bottom gate layer defining a groove, and a polish block layer being formed on the sidewall of the groove; forming an interlayer dielectric layer on the base on the side of the poly gate layer; removing the poly gate layer of the second region to form a gate opening; and forming a metal gate layer in the gate opening.