Polysilicon Gate Integration for Embedded Memory and Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing of embedded semiconductor devices, such as Flash memory, is hindered by expensive and time-consuming processes required to combine memory cores and logic gates into a single integrated circuit.
Innovation Solution
A semiconductor device design that includes a memory gate with a polycrystalline silicon layer over a charge trapping dielectric and a select gate adjacent to its sidewall, along with a logic gate in a separate region, utilizing specific etching and masking techniques to streamline the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory core and logic gates are combined into a single integrated circuit, then device functionality is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the integrated circuit into distinct first and second regions with different gate structures. The first region contains memory gates with charge trapping dielectric for non-volatile storage, while the second region contains logic gates with standard gate dielectric for processing operations. This segmentation allows each region to be optimized independently while maintaining a unified manufacturing process flow.
Solution Approach 2:
The patent employs a universal poly-silicon deposition process that forms gates for both memory and logic regions simultaneously. A single poly layer is deposited across the entire substrate, then selectively etched in different regions to create the appropriate gate structures. This multi-functional approach eliminates the need for separate manufacturing processes for memory and logic components.
2Adaptability or versatility
If memory core and logic gates are combined into a single integrated circuit, then device functionality is improved, but manufacturing time increases
Solution Approach 1:
The patent performs preliminary poly-silicon deposition across the entire substrate before regional differentiation. The charge trapping dielectric is formed in the first region prior to poly deposition, and the poly layer is deposited conformally over both memory and logic regions. This preliminary action establishes the foundation for both gate types simultaneously, reducing subsequent processing steps.
Solution Approach 2:
The manufacturing process maintains continuous poly-silicon deposition across the entire substrate without interrupting to switch between memory and logic region processing. The etching process continuously patterns both memory gates and logic gates from the same poly layer in a single operation, eliminating idle time and process interruptions.
3Reliability
If different gate structures are used for memory and logic regions, then device performance is improved, but manufacturing process difficulty increases
Solution Approach 1:
The patent implements local quality by forming charge trapping dielectric specifically in the first region where memory gates are required, while the second region maintains standard gate dielectric. The poly-silicon layer is then selectively etched in each region to create the appropriate gate structure. This localized differentiation allows optimized performance for each function while using a unified deposition process.
Solution Approach 2:
The patent changes material parameters locally by introducing charge trapping dielectric in the first region versus standard gate dielectric in the second region. The poly-silicon layer serves as a universal starting material that is then transformed into different gate structures through selective etching parameters. This parameter change approach enables diverse gate functionalities from a single material system.
Data Source
AI summary
A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.