Shared Poly Gate Tie-Off Layout for FinFET Isolation
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Solution Overview
Problem
In the development of vertical semiconductor devices like FinFETs, the increasing density of integrated circuits leads to electromagnetic interference between adjacent devices, and existing isolation methods are inefficient in maintaining device isolation without occupying additional device area.
Innovation Solution
Positioning a poly gate at the threshold voltage boundary and directly connecting it to a power rail using a conductive via to maintain the tie-off transistor in an off state, thereby electrically isolating adjacent transistors and optimizing device layout by eliminating the need for separate tie-off devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate tie-off devices are used for electrical isolation, then device isolation is achieved, but device area is increased
Solution Approach 1:
The patent combines the isolation function with the poly gate structure by positioning the poly gate at the threshold voltage boundary and connecting it to a power rail. This merging eliminates the need for separate tie-off devices, achieving electrical isolation while reducing device area occupation.
Solution Approach 2:
The poly gate structure is given dual functionality: it serves as both the gate for the transistor and the isolation device (tie-off device). By connecting the poly gate to the power rail via a conductive via, the same structure performs both switching and isolation functions, optimizing space utilization.
2Productivity
If device density is increased, then productivity is improved, but electromagnetic interference increases
Solution Approach 1:
The patent extracts the harmful electromagnetic interference by introducing isolation regions between adjacent devices. The poly gate positioned at the threshold voltage boundary acts as an isolation barrier, separating adjacent high-density devices and preventing electromagnetic interference while maintaining high device density.
3Reliability
If poly gate is connected to power rail, then tie-off transistor remains in off state, but additional manufacturing steps are required
Solution Approach 1:
The patent performs the isolation configuration during the existing poly gate formation process. The poly gate is positioned at the threshold voltage boundary and connected to the power rail through a conductive via as part of the standard fabrication sequence, ensuring the tie-off transistor is pre-configured in the off state before device operation.
Data Source
AI summary
An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.