Poly and Metal Gate Layout to Prevent CMP Dishing
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Solution Overview
Problem
The larger gate area of high voltage devices in semiconductor integrated circuits leads to dishing issues during Chemical Mechanical Polishing (CMP) processes, affecting the reliability and performance of the devices.
Innovation Solution
The use of a poly gate structure with a high selectivity during planarization processes, avoiding dishing issues by maintaining a larger gate area while using a dummy poly gate that is later replaced with a metal gate, ensuring compatibility with HKMG processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage devices with larger gate area are used, then device performance and reliability are improved, but dishing issues occur during CMP processes
Solution Approach 1:
The gate structure is segmented into two distinct parts: a metal gate for the low voltage device and a poly gate for the high voltage device. This segmentation allows each gate type to be optimized independently, with the poly gate specifically designed to prevent dishing during CMP while the metal gate provides high performance for low voltage operation.
Solution Approach 2:
Different gate structures are applied to different regions of the device based on local requirements. The poly gate with its specific material properties and geometry is used locally for high voltage devices where dishing prevention is critical, while metal gates are used for low voltage devices where performance is prioritized.
2Manufacturing precision
If poly gate structure with high selectivity is used during planarization, then dishing issues are avoided, but additional process steps are required
Solution Approach 1:
The poly gate structure is formed in advance with specific material properties that provide high selectivity during CMP planarization. This preliminary action ensures that the gate structure is already optimized for dishing prevention before the planarization process begins, eliminating the need for corrective measures later.
Solution Approach 2:
The poly gate acts as an intermediary structure between the substrate and the final metal gate. It provides the necessary mechanical and chemical properties for dishing-free planarization, while the metal gate is subsequently added to provide the final high-performance electrical characteristics.
3Adaptability or versatility
If dummy poly gate is used and later replaced with metal gate, then compatibility with HKMG processes is achieved, but process steps are increased
Solution Approach 1:
The poly gate structure serves multiple functions: it acts as a placeholder during early process stages, provides dishing-free planarization, and can be subsequently replaced with metal gate. This multi-functionality allows the same basic structure to be used across different device types and process variations, including HKMG processes.
Solution Approach 2:
The gate structure is designed to be dynamic and adaptable throughout the manufacturing process. The poly gate can be present during early stages for process compatibility, and then selectively replaced or modified in later stages to achieve the final desired configuration, allowing flexibility in process sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and performance of semiconductor devices by preventing dishing during planarization and maintaining device integrity, while being compatible with advanced manufacturing processes.
Implementation Method 1
The larger gate area of the high voltage devices results in dishing issue during the successive Chemical Mechanical Polishing (CMP) processes.
Data Source
AI summary
A semiconductor device includes a substrate, a metal gate and a poly gate. The substrate includes a first region and a second region. The metal gate is disposed on the first region of the substrate. The poly gate is disposed on the second region of the substrate. A gate area of the poly gate is greater than that of the metal gate.