Poly-Phase Sampling Rate Converter Circuit for Optical Systems
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Solution Overview
Problem
Existing sampling rate conversion methods in digital coherent optical communication systems require multiple circuits and complex settings for various sampling rates, leading to increased circuit scale and power consumption, and are not flexible enough to handle a wide range of transmission rates.
Innovation Solution
A sampling rate converter with a digital filter configured using poly-phase sub-filters, a route selection circuit, and a multiplexer that allows for easy conversion of input sampled signals to output sampled signals at arbitrary sampling rates by selecting appropriate sub-filters and output timings based on the conversion rate M/N, where M and N are integers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PLLs are mounted to cover a wide frequency variable range, then the frequency variable range is expanded, but power consumption increases and noise restrictions occur
Solution Approach 1:
A single PLL is designed to function universally across a wide frequency range by incorporating a variable frequency divider that can be controlled to achieve different division ratios. This allows one PLL to replace multiple PLLs, covering the entire required frequency variable range without increasing power consumption or introducing additional noise from multiple oscillators.
Solution Approach 2:
The PLL system employs dynamic control of the frequency divider ratio through digital signals. The division ratio can be changed in real-time based on the required output frequency, allowing the single PLL to adapt dynamically across its frequency range rather than requiring static multiple PLLs for different frequency bands.
2Adaptability or versatility
If multiple PLLs are mounted to cover a wide frequency variable range, then the frequency variable range is expanded, but the number of PLLs that can be mounted is restricted from a viewpoint of noise
Solution Approach 1:
A single PLL is designed to function universally across a wide frequency range by incorporating a variable frequency divider that can be controlled to achieve different division ratios. This allows one PLL to replace multiple PLLs, covering the entire required frequency variable range without increasing power consumption or introducing additional noise from multiple oscillators.
Solution Approach 2:
The functionality of multiple PLLs is merged into a single PLL system by combining the frequency synthesis capability with a controllable frequency divider. The multiple frequency generation functions are combined in one device through digital control of the division ratio, reducing the total number of PLL components while maintaining the ability to cover a wide frequency range.
3Ease of manufacture
If conventional sampling rate conversion is performed by M/N conversion, then the conversion is easy to realize, but a large-scale circuit is required
Solution Approach 1:
The sampling rate conversion process is segmented into two distinct stages: first, zero-insertion filtering where zero data is inserted between samples to create M times more data; second, decimation filtering where data is thinned out to obtain 1/N times less data. This segmentation allows each filtering stage to be optimized independently, reducing the overall circuit scale compared to performing a single complex M/N conversion.
Solution Approach 2:
The zero-insertion filtering is performed as a preliminary action before the main decimation filtering. By pre-processing the signal with zero insertion, the subsequent decimation filter operates on a structured signal pattern that simplifies its design and reduces its complexity. This preliminary action prepares the signal in a way that makes the final conversion more efficient and requires less circuit resources.
Data Source
AI summary
A sampling rate converter converting input signals d(i) (i=0, 1, 2, . . . ) sampled with an input sampling rate to output signals z(j) (j=0, 1, 2, . . . ) sampled with an output sampling rate that is M/N times the input sampling rate when M/N (M and N are integers equal to or larger than 1) is set as a conversion rate includes a digital filter configured with a plurality of sub-filters arranged in poly-phase, coefficients being set for the sub-filters, respectively, according to the conversion rate; route selection circuitry supplies each of the input signals inputted with the input sampling rate to at least one of the sub-filters of the digital filter according to the conversion rate; and a multiplexer outputting outputs of the plurality of sub-filters as the output signals with the output sampling rate in determined order according to the conversion rate.