Poly Resistor Implant for MOS Gate Doping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuits, the shrinking transistor dimensions lead to reduced dopant densities near gate oxides, resulting in increased polysilicon depletion and reduced on-state drive currents, which existing technologies struggle to address effectively.
Innovation Solution
The method involves using an ion implantation process to concurrently place dopant atoms into both polysilicon resistors and MOS transistor gates, allowing for the establishment of desired dopant concentrations in MOS transistor gates, enabling optimization of analog circuits without adding complexity or cost to the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are shrunk to follow Moore's Law, then integration density is improved, but dopant densities near gate oxides are reduced leading to increased polysilicon depletion and reduced on-state drive currents
Solution Approach 1:
The patent applies preliminary action by performing an ion implantation process to pre-dope the polysilicon gate with dopant atoms before transistor fabrication. This preliminary doping establishes a higher initial dopant concentration in the gate, which compensates for the reduced dopant densities that occur during subsequent processing steps. The pre-doped gate maintains sufficient dopant levels even as transistor dimensions are reduced, thereby preserving on-state drive currents while enabling continued scaling for improved integration density.
2Ease of manufacture
If ion implantation is used to dope polysilicon resistors, then resistor functionality is achieved, but additional process steps are required increasing fabrication complexity
Solution Approach 1:
The patent merges two separate ion implantation processes into a single concurrent operation. The same ion implantation step that doses the polysilicon gate is simultaneously used to dope the polysilicon resistor regions. By combining these two doping operations into one process step, the patent eliminates the need for a separate resistor doping step, thereby maintaining ease of manufacture while reducing fabrication process complexity.
Solution Approach 2:
The ion implantation process is given multi-functionality by using it to serve two purposes simultaneously: doping the polysilicon gate to establish proper threshold voltage and doping the polysilicon resistor to establish proper resistance values. This universal application of the ion implantation step eliminates the need for separate dedicated doping steps for each component, simplifying the overall fabrication process while maintaining the ease of manufacture for both transistor and resistor structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases on-state drive currents by reducing depletion regions in transistors, allows for different threshold voltages in transistors of the same IC, and maintains fabrication efficiency.
Implementation Method 1
an ion implantation process used to place dopant atoms into the polysilicon resistor is also used concurrently to place dopant atoms into a gate of the MOS transistor
Data Source
AI summary
A process of fabricating an IC is disclosed in which a polysilicon resistor and a gate region of an MOS transistor are implanted concurrently. The concurrent implantation may be used to reduce steps in the fabrication sequence of the IC. The concurrent implantation may also be used to provide another species of transistor in the IC with enhanced performance. Narrow PMOS transistor gates may be implanted concurrently with p-type polysilicon resistors to increase on-state drive current. PMOS transistor gates over thick gate dielectrics may be implanted concurrently with p-type polysilicon resistors to reduce gate depletion. NMOS transistor gates may be implanted concurrently with n-type polysilicon resistors to reduce gate depletion, and may be implanted concurrently with p-type polysilicon resistors to provide high threshold NMOS transistors in the IC.