Triple Poly-Si Replacement for Memory Top Oxide Quality
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Solution Overview
Problem
The miniaturization of semiconductor devices poses challenges in maintaining the quality of the top oxide layer, leading to charge leakage issues due to the scaling down of device dimensions, and existing methods risk damaging the periphery region when attempting to replace or reform the top oxide in memory devices.
Innovation Solution
A method involving the selective removal and reforming of the top oxide in the core region while protecting the periphery region, ensuring that the periphery first poly is not exposed to the core first poly removing process, and forming subsequent polysilicon layers to maintain uniform topography and improve the quality of the top oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the top oxide is replaced or reformed in the core region, then the quality of the top oxide is improved, but the periphery region may be damaged
Solution Approach 1:
The wafer is divided into core region and periphery region, with different processing applied to each. The core region undergoes top oxide removal and replacement, while the periphery region is protected from this process through selective masking and etching, thus resolving the contradiction between improving top oxide quality and preventing periphery damage
Solution Approach 2:
Different regions of the wafer are given different treatments: the core region receives aggressive top oxide removal and replacement to improve quality, while the periphery region maintains its original structure to avoid damage. This local differentiation allows simultaneous optimization of core performance and periphery integrity
2Productivity
If device dimensions are scaled down to achieve higher densities, then device packing density is improved, but charge leakage increases
Solution Approach 1:
The top oxide is removed and reformed with controlled thickness and quality parameters. By optimizing the oxide formation process parameters (temperature, time, atmosphere), the patent achieves thin but high-quality oxide layers that prevent charge leakage while allowing continued device scaling for higher density
Solution Approach 2:
A new top oxide layer is formed beforehand to protect the storage element from charge leakage. This preventive measure addresses the leakage issue that arises from scaling, cushioning against the harmful effects of reduced device dimensions before they can manifest as functional problems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of the top oxide by reducing charge leakage paths and maintaining uniformity between the core and periphery regions, simplifying subsequent fabrication processes and improving the overall performance of memory devices.
Implementation Method 1
thermal oxidation or deposition
Data Source
AI summary
A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions.