Poly-Si TFT Manufacturing Using Amorphous Silicon Connecting Layer
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Solution Overview
Problem
The complex and costly manufacturing process of poly-Si TFTs, which requires numerous exposure and ion implantation processes, results in low yield, high equipment investment, and poor compatibility with a-Si TFT production lines.
Innovation Solution
A TFT manufacturing method that uses an active layer with a poly-Si channel region and amorphous silicon source and drain regions, eliminating the need for ion implantation processes and simplifying the manufacturing process by using an amorphous silicon connecting layer for electrical connections, allowing for a bottom-gate structure and reduced exposure processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional poly-Si TFT manufacturing process is used, then high electron mobility is achieved, but the manufacturing process becomes complex with numerous exposure and ion implantation processes
Solution Approach 1:
The patent changes the material parameter of the source and drain regions from poly-Si to amorphous silicon, which fundamentally alters the manufacturing requirements. This parameter change eliminates the need for ion implantation processes while maintaining the ability to achieve high electron mobility through laser annealing of the channel region only.
Solution Approach 2:
The patent extracts and removes the ion implantation processes from the manufacturing flow, which were previously necessary for doping source and drain regions. By using amorphous silicon that is deposited in an amorphous state and then selectively crystallized, the complex ion implantation steps are completely eliminated, simplifying the process while maintaining device performance.
2Reliability
If conventional poly-Si TFT manufacturing process is used, then active layer is formed, but equipment investment increases and yield decreases
Solution Approach 1:
The patent makes the manufacturing process universal by using amorphous silicon deposition, which is a standard process in a-Si TFT production lines. This allows the same production line to manufacture both a-Si and poly-Si TFTs without requiring specialized ion implantation equipment, reducing equipment investment and improving compatibility across different product lines.
Solution Approach 2:
The patent skips the time-consuming ion implantation and multiple annealing steps by using a direct laser annealing approach on amorphous silicon. The laser annealing process rapidly crystallizes only the channel region, skipping intermediate doping and annealing steps, which reduces manufacturing time and improves yield.
3Reliability
If conventional poly-Si TFT manufacturing process is used, then channel region is formed, but compatibility with a-Si TFT production line deteriorates
Solution Approach 1:
The patent changes the crystallization parameter from bulk crystallization (requiring high-temperature furnaces) to selective laser-induced crystallization. This parameter change allows the process to be performed at lower temperatures and with localized energy input, making it compatible with existing a-Si TFT production lines that lack high-temperature furnaces and ion implantation equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces equipment investment, improves compatibility with a-Si TFT production lines, and maintains high electron mobility and low OFF-state leakage current, making it suitable for high-generation production lines.
Implementation Method 1
performing a laser annealing treatment on a region to be formed as an active layer of an amorphous silicon film
Implementation Method 2
high-temperature processes such as dehydrogenation, hydrogenation and activation
Data Source
Figure 1~3
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Figure 6~7
AI summary
Embodiments of the present invention relate to a thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device. The TFT (100) comprises an active layer (110), an amorphous silicon (a-Si) connecting layer (120) and a source-drain electrode layer (130). The active layer (110) includes a channel region (113), a source region (111) and a drain region (112); forming materials of the channel region (113) include polycrystalline silicon (poly-Si); the a-Si connecting layer (120) is disposed on a side of the active layer (110) and includes a first connecting part (121) and a second connecting part (122) which are spaced from each other; the source-drain electrode layer (130) includes a source electrode (131) and a drain electrode (132) which are spaced to each other; the source electrode (131) is electrically connected with the source region (111) through the first connecting part (121); and the drain electrode (132) is electrically connected with the drain electrode (112) through the second connecting part (122). The present disclosure can simplify the manufacturing process of a poly-Si TFT.