Poly-Si TFT with Dual-Layer Doping for Leakage Reduction
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Solution Overview
Problem
The manufacturing process of Poly-Si TFTs with a bottom gate structure is complex and costly due to the requirement of a lightly doped drain (LDD) structure, which necessitates additional photolithography and ion implantation processes, and applying these TFTs to large-sized panels is challenging due to non-uniformity in laser crystallization.
Innovation Solution
A Poly-Si TFT with a bottom gate structure is manufactured using a method that includes forming doped Poly-Si layers with specific impurity concentrations, where the first Poly-Si layers are doped with a low concentration and the second Poly-Si layers are doped with the same or higher concentration, and the LDD regions are formed without overlapping with the gate electrode, eliminating the need for additional photolithography and ion implantation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a bottom gate structure is used for Poly-Si TFT manufacturing, then cost reduction is advantageous, but additional photolithography and ion implantation processes are required to form LDD structure
Solution Approach 1:
The patent combines the LDD formation and source/drain electrode formation into a single integrated process. The doped Poly-Si layers serve dual purposes: they create the LDD regions with appropriate doping concentrations and simultaneously function as the source and drain electrodes, eliminating the need for separate electrode deposition and patterning steps.
Solution Approach 2:
The doped Poly-Si layers perform multiple functions: they act as LDD regions for leakage current reduction, serve as source and drain electrodes for device operation, and provide structural definition for the transistor. This multi-functionality reduces the total number of process steps required.
2Reliability
If laser crystallization is used for Poly-Si formation, then high mobility is achieved, but non-uniformity occurs making large-sized panel application difficult
Solution Approach 1:
The patent replaces laser-based crystallization with a different approach where amorphous silicon layers are deposited with controlled doping concentrations and then thermally annealed. This substitution of the crystallization method eliminates the non-uniformity issues associated with laser processing while maintaining the Poly-Si structure necessary for high mobility.
3Object-generated harmful factors
If LDD structure is formed with additional photolithography and ion implantation processes, then leakage current is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent performs preliminary doping during the Poly-Si layer deposition process itself, incorporating dopants at controlled concentrations before the layers are crystallized. This preliminary action creates the LDD regions with appropriate doping profiles without requiring subsequent ion implantation steps, as the doping is established during the formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, reduces costs, and achieves a Poly-Si TFT with reduced leakage current, enabling the production of Poly-Si TFTs suitable for large-sized panels without the need for complex LDD formation.
Implementation Method 1
crystallizing the amorphous silicon layer and the first and second amorphous silicon layers
Implementation Method 2
The amorphous silicon layer and the first and second amorphous silicon layers may be crystallized by furnace annealing
Data Source
AI summary
Provided may be a Poly-Si thin film transistor (TFT) and a method of manufacturing the same. The Poly-Si TFT may include a first Poly-Si layer on an active layer formed of Poly-Si and doped with a low concentration; and a second Poly-Si layer on the first Poly-Si layer and doped with the same concentration as the first Poly-Si layer or with a higher concentration than the first Poly-Si layer, wherein lightly doped drain (LDD) regions capable of reducing leakage current may be formed in inner end portions of the first Poly-Si layer.