Poly-SiGe Capacitor Electrodes for Leakage Reduction
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Solution Overview
Problem
In highly integrated semiconductor devices, such as DRAM capacitors, the use of high-k dielectric layers can react with doped polysilicon electrodes, leading to degraded electrical characteristics and increased leakage current, while attempts to mitigate this with low-k dielectric layers or metal electrodes result in suboptimal performance due to low resistivity and thermal instability.
Innovation Solution
The implementation of a poly-Si1-xGex layer with a Ge content between 0.1 and 0.7, which is formed at temperatures between 350°C and 550°C, acts as a doped upper electrode in capacitors, reducing the need for annealing and improving resistivity, thereby minimizing leakage current and thermal degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a doped polysilicon electrode is used with a high-k dielectric layer, then the capacitor can achieve high cell capacitance in a small area, but the electrical characteristics of the capacitor are degraded due to reaction between the poly-Si electrode and the high-k dielectric layer
Solution Approach 1:
A low-k dielectric layer (such as SiON layer) is introduced as an intermediary barrier layer between the doped polysilicon electrode and the high-k dielectric layer. This intermediate layer prevents direct reaction between the poly-Si electrode and the high-k dielectric material, thereby maintaining the electrical characteristics of the capacitor while still allowing the high-k dielectric to provide high capacitance density.
Solution Approach 2:
The capacitor structure employs a composite dielectric system combining low-k dielectric material (SiON) and high-k dielectric material in a layered configuration. This composite structure leverages the advantages of both materials: the low-k layer provides chemical stability and prevents degradation, while the high-k layer delivers high capacitance in a compact form factor.
2Reliability
If a low-k dielectric layer is added between the doped poly-Si electrode and the high-k dielectric layer to prevent reaction, then the electrical characteristics are improved, but the thickness of the capacitor dielectric layer substantially increases
Solution Approach 1:
The thickness of the low-k dielectric barrier layer is precisely controlled within a narrow range (50-200 nm) to provide adequate chemical protection while minimizing the increase in overall capacitor thickness. By optimizing this critical parameter, the invention achieves a balance between preventing electrode-dielectric reactions and maintaining compact capacitor dimensions suitable for high-density memory devices.
3Reliability
If a metal layer is used as the upper electrode to reduce reactivity with high-k dielectric, then the reactivity is reduced, but the metal layer cannot readily function as a resistor layer for delaying signals due to its low resistivity
Solution Approach 1:
The upper electrode is constructed as a composite structure combining a metal layer (such as TiN) with a doped polysilicon layer. The metal layer provides chemical stability and low reactivity with the high-k dielectric, while the doped polysilicon layer contributes higher resistivity to enable signal delay functionality. This composite electrode structure simultaneously satisfies both the reactivity reduction requirement and the signal delay capability.
4Reliability
If a doped poly-Si layer is deposited and annealed to activate the layer for use as an upper electrode, then the electrode functionality is improved, but the leakage current of the capacitor increases
Solution Approach 1:
The deposition temperature of the doped polysilicon layer is reduced to 550°C or lower, which is below the conventional annealing temperature range. This parameter change allows the layer to be deposited in an activated state with adequate crystallinity and electrical properties, eliminating or reducing the need for subsequent high-temperature annealing processes that would otherwise increase capacitor leakage current.
Solution Approach 2:
The deposition process is designed to continuously produce an activated, functional polysilicon layer without interruption by a separate annealing step. By maintaining the useful action of creating an electrically active electrode material throughout the deposition process itself, the invention avoids the energy loss and leakage current increase associated with traditional annealing cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of semiconductor devices with reduced leakage current and improved thermal stability, enabling the formation of capacitors with enhanced electrical characteristics at lower temperatures, thus addressing the limitations of existing technologies.
Implementation Method 1
a poly-Si1-xGex layer which is doped and has a Ge content between 0.1 and 0.7
Data Source
AI summary
A semiconductor device includes a lower electrode of a capacitor, a dielectric layer disposed on the lower electrode, and an upper electrode of the capacitor disposed on the dielectric layer. The upper electrode includes a doped poly-Si1-xGex layer. An interlayer insulating layer is disposed on the doped poly-Si1-xGex layer and has a contact hole partially exposing the doped poly-Si1-xGex layer. A metal contact plug is in the contact hole and an interconnection layer is disposed on the interlayer insulating layer and connected to the metal contact plug. Related interconnection structures and fabrication methods are also disclosed.