Polycrystalline Silicon Activation RTA for SRAM Yield
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Solution Overview
Problem
In semiconductor manufacturing, particularly for SRAM integrated circuits, variations in transistor threshold voltages lead to significant single bit failures due to improper dopant distribution at the gate layer interface, resulting in zero SRAM IC product yield, especially as critical dimensions decrease below 100 nm.
Innovation Solution
The method involves rapid thermal annealing of the gate stack at temperatures of at least 950°C, followed by forming source/drain regions, and includes separate gate layer activation before source/drain implantation, with optional slow annealing to prevent dopant loss and bubble formation, and selective oxidation to maintain interface integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single implant activation step is used for both source/drain regions and gate layer, then processing time is reduced, but dopant distribution at the gate layer interface becomes improper leading to threshold voltage variations
Solution Approach 1:
The patent divides the single activation step into two separate activation steps: first activating the gate layer at a lower temperature (700-800°C) before source/drain implantation, and then activating source/drain regions at a higher temperature (900-1000°C). This segmentation allows independent optimization of dopant distribution for each region, resolving the contradiction between processing time and dopant distribution precision.
2Manufacturing precision
If rapid thermal annealing is performed at high temperature (≥950°C) to activate gate layer, then dopant distribution is improved, but nitrogen loss from refractory layer occurs causing layer merging
Solution Approach 1:
The patent performs gate layer activation before source/drain implantation and before forming sidewall oxide. By completing the gate layer activation in advance at controlled temperatures, the refractory layer nitrogen is preserved, preventing unwanted merging with the metal layer while still achieving proper dopant distribution in the gate layer.
Solution Approach 2:
The patent changes the temperature parameter by performing activation at different stages: first at 700-800°C for gate layer activation, then at 900-1000°C for source/drain activation. This parameter change allows achieving proper dopant distribution without exceeding the temperature threshold that would cause nitrogen loss from the refractory layer.
3Length of moving object
If critical dimensions are reduced below 100 nm to increase device density, then transistor scaling is achieved, but threshold voltage variations increase leading to single bit failures
Solution Approach 1:
The patent performs preliminary gate layer activation before source/drain implantation to ensure proper dopant distribution at the gate layer interface. This preliminary action is critical for maintaining consistent threshold voltages in scaled devices with gate lengths below 100 nm, preventing single bit failures and improving SRAM device yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the static noise margin and reduces the standard deviation of threshold voltages in SRAM devices, improving yield and reliability by ensuring proper dopant distribution and interface stability.
Implementation Method 1
rapid thermal annealing of a gate stack on a semiconductor substrate at a temperature of at least 950° C.
Implementation Method 2
activating the gate layer
Implementation Method 3
the gate layer 112′ of the gate electrode 200 is selectively oxidized, to form sidewall oxide 170
Data Source
AI summary
A method of forming a semiconductor structure includes rapid thermal annealing of a gate stack on a semiconductor substrate at a temperature of at least 950° C., followed by forming source/drain regions in the semiconductor substrate.