Poly-Silicon Alloy Gate Electrode for Submicron Semiconductor Devices
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Solution Overview
Problem
In semiconductor devices, particularly in submicron generations, poly-Si gates face challenges due to the poly depletion effect and high electrical sheet resistance, as well as dopant diffusion issues, which hinder performance improvements and scaling.
Innovation Solution
A semiconductor device structure is developed with a gate stack comprising a metal gate electrode and a top gate electrode layer made of a poly-silicon alloy, such as poly-silicon germanium (SiGe), which reduces resistance and improves gate control, while maintaining uniformity and reducing thermal budget requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If poly-Si gate is used in submicron devices, then device fabrication is simplified, but device performance degrades due to poly depletion effect and high electrical sheet resistance
Solution Approach 1:
The patent employs a composite gate structure combining metal gate electrode (such as tungsten) with poly-Si gate material. This composite approach leverages the low resistance properties of metal while maintaining the fabrication compatibility of poly-Si, thereby resolving the contradiction between ease of manufacture and device performance in submicron devices
2Reliability
If dopants are added to poly-Si gate to reduce resistance, then electrical sheet resistance decreases, but dopant diffusion through gate dielectric increases causing performance degradation
Solution Approach 1:
The patent introduces an intermediary metal gate electrode layer between the poly-Si gate and the gate dielectric. This metal layer serves as a barrier that prevents dopant diffusion while providing low resistance pathways, thus reducing electrical sheet resistance without causing dopant diffusion issues
3Manufacturing precision
If high-K material is used to increase gate dielectric capacitance, then equivalent oxide thickness decreases without reducing physical thickness, but oxygen diffusion causes unwanted dielectric growth and geometry impairment
Solution Approach 1:
The patent uses the metal gate electrode as an intermediary barrier between the high-K dielectric material and the oxygen environment. This metal layer prevents oxygen diffusion into the high-K material, eliminating unwanted dielectric growth and geometry impairment while maintaining the benefits of reduced equivalent oxide thickness
4Manufacturing precision
If gate dielectric thickness is increased to use high-K material, then equivalent oxide thickness improves, but drain currents decrease and gate length scaling is limited
Solution Approach 1:
The patent combines metal gate electrode with high-K dielectric material to create a composite gate structure. This combination allows the use of thicker high-K dielectric for improved EOT while the metal gate component maintains strong electrostatic control, preventing drain current degradation and enabling continued gate length scaling
Data Source
AI summary
A method of forming a semiconductor device is presented. The method includes providing a substrate. The method further includes forming a gate stack having a gate electrode on the substrate, which includes forming a metal gate electrode layer. A buffer gate electrode layer is formed on top of the metal gate electrode layer and a top gate electrode layer having a poly-silicon alloy is formed over the metal gate electrode layer.