Polycrystalline Silicon Backside Roughness for EUV Wafer Clamping
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Solution Overview
Problem
Current EUV lithography processes face challenges in uniformly distributing pressure on semiconductor wafers during processing, leading to stress and irregularities due to static electrical forces used by electrostatic chucks, which are not effectively alleviated by existing methods.
Innovation Solution
A polycrystalline silicon layer with enhanced surface roughness is formed on the backside of the wafer to reduce clamping effects by creating spacing between the wafer and the electrostatic chuck, allowing gas to flow and distribute pressure more uniformly, thereby mitigating stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Force
If gas is pumped through the E-chuck to the backside of the wafer to relieve static electrical force, then the force on the wafer is reduced, but the pressure is not uniformly distributed and stress builds up
Solution Approach 1:
The patent applies local quality by creating non-uniform surface roughness on the wafer backside with specific peak and valley structures. This local structural modification allows gas to accumulate in valley regions and directs flow paths, creating localized pressure zones that collectively achieve uniform overall pressure distribution across the wafer surface.
Solution Approach 2:
The patent implements preliminary action by pre-forming the polycrystalline silicon layer with enhanced surface roughness on the wafer backside before the EUV lithography process. This pre-structured surface topology prepares the wafer to receive and distribute gas pressure uniformly during the subsequent lithography operation, preventing stress buildup from the outset.
2Reliability
If a smooth wafer backside is used with E-chuck, then the wafer is securely held, but stress and irregularities occur due to concentrated clamping force
Solution Approach 1:
The patent modifies the local quality of the wafer backside surface by depositing a polycrystalline silicon layer with controlled surface roughness featuring peaks and valleys. This creates localized contact points that maintain secure holding while distributing clamping forces, preventing stress concentration and resulting wafer surface irregularities.
Solution Approach 2:
The polycrystalline silicon layer acts as an intermediary between the wafer and the E-chuck. This intermediate layer with its roughened surface topology mediates the interaction by distributing the electrostatic clamping force across multiple contact points, thereby maintaining secure holding while preventing direct stress concentration on the wafer.
3Stress or pressure
If uniform pressure distribution is achieved, then stress on wafer is reduced, but requires complex gas distribution system
Solution Approach 1:
The patent implements self-service by designing the wafer backside surface structure itself to perform the pressure distribution function. The polycrystalline silicon layer with its inherent peak and valley topology automatically guides gas flow and distributes pressure uniformly without requiring external complex distribution mechanisms, simplifying the overall system.
Solution Approach 2:
The patent changes the physical parameter of the wafer backside surface from smooth to roughened with specific peak and valley dimensions. This parameter change in surface topology transforms the gas flow characteristics, enabling natural pressure equalization across the wafer surface through the structured surface features alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced surface roughness of the polycrystalline silicon layer effectively reduces the clamping effect during EUV lithography, ensuring more uniform pressure distribution and minimizing stress on the wafer, thereby improving processing accuracy and reducing irregularities.
Implementation Method 1
An E-chuck includes a charged plate that uses static electrical forces to secure the semiconductor wafer to the chuck
Implementation Method 2
This gas is pressurized to provide an opposing force to the static electrical force
Data Source
AI summary
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.