Polycrystalline Silicon Graphene Transistor Active Layer
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Solution Overview
Problem
Transistors using amorphous silicon or polysilicon face challenges such as reduced mobility, increased threshold voltage distribution, and bias current reduction, which affect the reliability and performance of display devices like OLEDs and LCDs, requiring additional circuits for compensation.
Innovation Solution
A transistor design incorporating an active layer with a double structure, featuring a polycrystalline silicon layer and a graphene layer pattern, where the graphene is buried within the silicon, enhancing electrical characteristics and allowing for better control of the active layer, thereby improving reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon or polysilicon is used as the active layer material, then the transistor can be manufactured with existing processes, but the mobility is reduced and threshold voltage distribution increases
Solution Approach 1:
The active layer is formed as a composite structure combining polycrystalline silicon and graphene. The polycrystalline silicon provides a manufacturable base layer using existing semiconductor processes, while the integrated graphene component enhances carrier mobility and stabilizes threshold voltage, thus resolving the contradiction between ease of manufacture and device reliability
Solution Approach 2:
The invention changes the material composition parameters of the active layer by incorporating graphene into the polycrystalline silicon matrix. This parameter change increases carrier mobility from typical polysilicon values to higher levels, while also reducing threshold voltage distribution, thereby improving reliability without sacrificing manufacturability
2Device complexity
If conventional active layer materials are used, then the device structure remains simple, but bias current is reduced and performance deteriorates
Solution Approach 1:
The active layer employs a composite of polycrystalline silicon and graphene, where the graphene component specifically targets performance enhancement by providing high carrier mobility channels. This composite approach increases bias current and overall transistor performance while maintaining a relatively simple layered structure that does not excessively increase device complexity
Solution Approach 2:
The graphene is strategically positioned within specific regions of the active layer to locally enhance carrier transport properties. This local quality improvement focuses the performance enhancement where it is most needed for bias current flow, achieving higher productivity without requiring complete structural redesign of the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed transistor structure enhances electrical characteristics, reducing threshold voltage distribution, increasing mobility, and maintaining bias current, leading to improved display device performance with reduced thickness and increased image resolution and operating speed.
Implementation Method 1
irradiating a laser onto the preliminary graphene layer and the amorphous silicon layer
Implementation Method 2
irradiating a first laser onto the preliminary graphene layer to melt the preliminary graphene layer into the amorphous silicon layer
Implementation Method 3
irradiating a second laser onto the amorphous silicon layer to crystallize the amorphous silicon layer into a polycrystalline silicon layer
Data Source
AI summary
A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern.