Poly-Silicon Oxide TFT Array Substrate Slim Edge Frame
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Solution Overview
Problem
Current display technologies face challenges in achieving slim edge-frame designs, which limit the screen ratio and displaying performance due to larger non-display areas in display devices.
Innovation Solution
The development of an array substrate with a small size, featuring a first thin-film transistor and a second thin-film transistor arranged in parallel on a base, where the second transistor is formed simultaneously with the first, using poly-silicon and oxide semiconductor materials respectively, to reduce the size of the thin-film transistor and increase the display area, and the use of a manufacturing method that includes forming a buffer layer, patterning, and ion activation/hydrogenation to enhance transistor efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate fabrication processes are used for different thin-film transistors, then manufacturing precision can be maintained, but manufacturing complexity and time increase
Solution Approach 1:
The patent merges the fabrication processes for the first and second thin-film transistors into a single integrated process. The poly-silicon layer is formed once and then patterned to create both the first active layer and the second gate electrode simultaneously. This combining of operations reduces manufacturing complexity while maintaining precision through the unified process design.
Solution Approach 2:
The poly-silicon layer serves multiple functions: it forms the active layer of the first transistor and the gate electrode of the second transistor. This multi-functionality eliminates the need for separate material deposition steps for each component, simplifying the overall manufacturing process while ensuring consistent material properties across different transistor types.
2Reliability
If larger non-display areas are used for transistor placement, then device functionality is ensured, but screen ratio and display performance decrease
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) by forming the second gate electrode on top of the first active layer structure. This three-dimensional arrangement allows transistor components to be stacked vertically rather than spread horizontally, reducing the footprint in the non-display area while maintaining all necessary electrical connections and functionality.
Solution Approach 2:
The structure nests the second gate electrode within the same planar footprint as the first transistor by positioning it above the first active layer. This nesting arrangement allows both transistor components to share the same horizontal space, minimizing the non-display area required while ensuring complete device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the display area and aperture ratio, reduces the non-display area, and improves the manufacturing efficiency by eliminating the need for separate fabrication of the second thin-film transistor, thereby achieving a slimmed edge frame and enhanced displaying performance.
Implementation Method 1
subjecting amorphous materials of the first active layer and the first gate electrode to ion activation/hydrogenation
Implementation Method 2
subjecting amorphous materials of the first active layer and the first gate electrode to ion activation/hydrogenation
Data Source
AI summary
An array substrate includes first and second thin-film transistors formed on a base and spaced by a predetermined distance in a first direction that is parallel to the plane on which the base is located and set in parallel. The first thin-film transistor includes a first active layer, a first gate insulation layer, a first gate electrode, a first interlayer insulation layer, and first source/drain electrodes sequentially stacked on the base in a third direction that is perpendicular to the first direction. The first source/drain electrodes are electrically connected to the first active layer. The second thin-film transistor includes a second gate electrode, a second gate insulation layer, second source/drain electrodes, and a second active layer sequentially stacked on the base in the third direction. The first active layer and the first gate electrode are both formed of a poly-silicon material. The second active layer includes an oxide semiconductor material.