Poly-Silicon Pixel Circuit Layout for Compact High-Resolution Displays
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Solution Overview
Problem
Existing display devices face challenges in reducing the area of pixel circuits while maintaining high resolution and improving transistor performance, particularly in achieving efficient light emission through optimized transistor types.
Innovation Solution
The implementation of a pixel circuit with a PMOS transistor and an NMOS transistor, where each transistor is formed using polycrystalline silicon doped with different impurities, specifically boron for the PMOS and phosphorus for the NMOS, allows for reduced pixel circuit area and enhanced resolution by utilizing distinct active patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing transistor designs are used in pixel circuits, then the circuit can be manufactured with standard processes, but the area occupied by the pixel circuit is large and resolution is limited
Solution Approach 1:
The patent merges the PMOS and NMOS transistor designs into a unified polycrystalline silicon structure with differentiated doping regions. Both transistor types share the same semiconductor layer and manufacturing process steps, reducing overall circuit area while maintaining standard manufacturing compatibility.
Solution Approach 2:
The patent applies local quality by using the same polycrystalline silicon material throughout but differentiating specific regions through selective doping. The first region receives P-type doping for PMOS while the second region receives N-type doping for NMOS, allowing compact integration with optimized local properties for each transistor type.
2Reliability
If polycrystalline silicon doped with P-type and N-type impurities is used, then leakage current is reduced and electron mobility is enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent changes the doping parameter (impurity type) selectively across different regions of the polycrystalline silicon. By controlling the doping concentration and type (P-type or N-type) in specific regions, the invention achieves low leakage current and enhanced electron mobility without fundamentally changing the manufacturing process flow.
Solution Approach 2:
The patent creates a composite doped polycrystalline silicon structure where P-type and N-type doped regions are integrated within the same material matrix. This composite approach allows the material to exhibit different electrical properties in different regions while maintaining structural uniformity and simplifying manufacturing.
3Area of moving object
If compact transistor configuration is implemented, then pixel circuit area is reduced and resolution is improved, but light emission efficiency may be compromised
Solution Approach 1:
The patent implements a compact dynamic logic circuit configuration where the PMOS and NMOS transistors are arranged in a space-efficient manner with shared connections. The dynamic operation of the transistors maintains high switching efficiency and light emission performance while occupying minimal pixel area, enabling both compactness and efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces leakage current in PMOS transistors and improves electron mobility in NMOS transistors, leading to efficient light emission and improved display device resolution.
Implementation Method 1
a first terminal including polycrystalline silicon doped with a first impurity
Implementation Method 2
reduces leakage current
Implementation Method 3
a third terminal including polycrystalline silicon doped with a second impurity different from the first impurity
Implementation Method 4
enhances electron mobility
Implementation Method 5
a light-emitting diode including an anode terminal electrically connected to the second terminal and a cathode terminal electrically connected to a second voltage
Implementation Method 6
improve light emission efficiency
Data Source
AI summary
A pixel circuit includes a first transistor a first gate terminal electrically connected to a gate node, a first terminal including polycrystalline silicon doped with a first impurity and electrically connected to a first voltage and a second terminal including polycrystalline silicon doped with the first impurity, and a second transistor a second gate terminal electrically connected to a first gate signal, a third terminal including polycrystalline silicon doped with a second impurity and electrically connected to the gate node and a fourth terminal including polycrystalline silicon doped with the second impurity.