Polycrystalline Silicon TFT Fabrication via Catalyst Extraction
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Solution Overview
Problem
Existing methods for crystallizing amorphous silicon into polycrystalline silicon, such as metal-induced lateral crystallization (MILC), face challenges in effectively removing catalyst metals from the semiconductor layer, leading to electrical leakage and adhesion issues between the gate electrode and gate insulating layer, which deteriorate the quality of thin film transistors in liquid crystal display devices.
Innovation Solution
A method that forms an amorphous silicon pattern on a substrate, followed by a catalyst metal pattern, annealing to convert the amorphous silicon into polycrystalline silicon, and then removing the catalyst metal by etching or polishing to prevent adhesion loss and electrical leakage, while forming a gate electrode and insulating layers to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MILC method is used to crystallize amorphous silicon into polycrystalline silicon, then production yield increases and treatment time is reduced, but catalyst metal remains in the silicon layer causing electrical leakage
Solution Approach 1:
The patent extracts the harmful catalyst metal from the polycrystalline silicon layer through selective etching processes. After the MILC crystallization process completes, etching treatments are applied to remove residual metal catalysts from the silicon layer, thereby eliminating the source of electrical leakage while preserving the beneficial polycrystalline structure
Solution Approach 2:
The patent converts the harmful presence of catalyst metal into a beneficial process by utilizing controlled etching steps. The etching processes selectively remove the metal catalysts that caused electrical leakage problems, transforming the harmful residual metal into a removable byproduct while maintaining the improved crystallization benefits
2Productivity
If MILC method is used to crystallize amorphous silicon, then production efficiency improves, but adhesion between gate electrode and insulating layer deteriorates due to void formation
Solution Approach 1:
The patent removes voids and defects formed during MILC processing through controlled etching and cleaning steps. By extracting these harmful voids from the interface regions between the gate electrode and insulating layer, the adhesion strength is restored while maintaining the production efficiency benefits of MILC
Solution Approach 2:
The patent applies preliminary etching and cleaning treatments after crystallization but before final device assembly. These preliminary actions remove potential adhesion problems early in the process, preventing void formation from compromising the gate electrode-to-insulating layer bonding in subsequent steps
3Ease of manufacture
If catalyst metal is not removed from polycrystalline silicon layer, then manufacturing process is simpler, but electrical leakage occurs in thin film transistor channel
Solution Approach 1:
The patent introduces intermediary etching processes as mediating steps between crystallization and device fabrication. These intermediary treatments selectively remove catalyst metals without requiring complete process redesign, adding moderate complexity while effectively eliminating electrical leakage issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high-quality polycrystalline silicon semiconductor layers with improved adhesion between the gate electrode and insulating layers, reducing voids and electrical leakage, thereby enhancing the performance and yield of thin film transistors in liquid crystal display devices.
Implementation Method 1
a catalyst metal pattern 191a and 191b are formed on the amorphous silicon pattern 120... annealing in a furnace at a temperature between 300 and 500 degrees Celsius to cause a reaction between the amorphous silicon and the catalyst metal layer 190
Implementation Method 2
annealing in a furnace at a temperature between 300 and 500 degrees Celsius
Implementation Method 3
the catalyst metal 192 is removed by etching or chemical mechanical polishing a part of the surface of the polycrystalline silicon pattern 121
Data Source
AI summary
A method of fabricating an array substrate for a liquid crystal display device is provided. The method includes steps of forming an amorphous silicon pattern on a substrate; forming a catalyst metal pattern on the amorphous silicon pattern; annealing the amorphous silicon pattern to be converted into a polycrystalline silicon pattern using the catalyst metal pattern as a catalyst; forming a gate insulating layer on the polycrystalline silicon pattern; forming a gate electrode on the gate insulation layer at a position corresponding to the polycrystalline silicon pattern; doping the polycrystalline silicon pattern with impurities using the gate electrode as a doping mask to form an ohmic contact layer and an active layer; forming an interlayer insulating layer having first and second contact holes on the gate electrode, the first and second contact holes exposing portions of the ohmic contact layer; and forming a source electrode and a drain electrode on the interlayer insulating layer, the source electrode and the drain electrode connected to the ohmic contact layer respectively through the first and second contact holes.