Low-Temperature Poly-Silicon TFT Array Substrate Lithography Reduction
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Solution Overview
Problem
The production of low temperature polycrystalline silicon field effect thin film transistor array substrates is complex and costly due to the high number of lithographic processes required, leading to long process times and low yields in conventional methods.
Innovation Solution
A method reducing the number of lithographic processes by using a stepped photo resist process, film peeling, and simultaneous deposition of gate and source/drain electrodes, combining multiple steps into fewer processes, such as forming a polycrystalline silicon active layer and storage capacitor, gate electrode, and pixel electrode in fewer lithographic steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to form polycrystalline silicon active layer, storage capacitor, gate electrode, and pixel electrode separately, then each component can be precisely formed, but the production process becomes complex and time-consuming
Solution Approach 1:
The patent combines the formation of polycrystalline silicon active layer and storage capacitor into a single lithographic process by using a multi-layer photoresist structure. The first photoresist layer patterns the active layer, while the second photoresist layer patterns the storage capacitor, both simultaneously exposed and developed in one step, eliminating separate lithography steps for each component.
Solution Approach 2:
The patent makes the photoresist layers serve multiple functions: the first photoresist layer acts as both the patterning mask for the active layer and as a support layer during subsequent processing. The second photoresist layer serves as the patterning mask for the storage capacitor and can be used to define other structures. This multi-functionality reduces the total number of lithographic steps required.
2Manufacturing precision
If multiple separate lithographic processes are used for forming different components, then each component can be optimized independently, but the production time increases and yield decreases
Solution Approach 1:
The patent performs preliminary patterning of the polycrystalline silicon layer for both the active layer and storage capacitor in one simultaneous lithographic step. The multi-layer photoresist structure allows both components to be defined before subsequent processing steps, enabling parallel optimization of both components while reducing the total number of sequential steps.
Solution Approach 2:
The patent maintains continuous processing by combining multiple patterning operations into a single lithographic exposure and development cycle. The multi-layer photoresist structure allows simultaneous definition of multiple components without breaking the processing flow, maintaining momentum and reducing idle time between steps.
3Manufacturing precision
If conventional multi-step lithographic processes are used, then complex structures can be formed, but the production cost increases
Solution Approach 1:
The patent merges multiple lithographic steps into a single process by using a multi-layer photoresist structure that allows simultaneous patterning of the polycrystalline silicon active layer and storage capacitor. This consolidation reduces equipment usage, material consumption, and labor costs associated with multiple separate lithography steps while maintaining the ability to form complex structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the production process, reduces costs, and improves yield by minimizing the number of lithographic processes to four, enhancing the efficiency and cost-effectiveness of producing low temperature polycrystalline silicon field effect thin film transistor array substrates.
Implementation Method 1
By means of Excimer Laser Annealing (ELA) or solid phase crystallization (SPC), the α-Si may be crystallized into a polycrystalline silicon film
Implementation Method 2
By means of Excimer Laser Annealing (ELA) or solid phase crystallization (SPC), the α-Si may be crystallized into a polycrystalline silicon film
Implementation Method 3
a pattern in a layer of photo resist is formed on the polycrystalline silicon film by the conventional patterning process
Implementation Method 4
the portion of the polycrystalline silicon film that is not shielded is etched by plasma to form a polycrystalline silicon active layer 4 and a polycrystalline silicon storage capacitor 3
Implementation Method 5
Low concentration ion implantation is carried out in the transistor channel in the polycrystalline silicon active layer 4 by ion implantation process
Implementation Method 6
a SiO 2 film or a composite film of SiO 2 and SiN is deposited by PECVD
Implementation Method 7
One or more low resistance metal material film is deposited on the gate insulation layer 6 by physical vapor deposition process such as magnetron sputtering
Data Source
Figure 1~2B
Figure 2C~2E
Figure 2F~2G
AI summary
The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.