Polycrystalline TFT Leakage Current Reduction via Impurity Control
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Solution Overview
Problem
Polycrystalline silicon thin film transistors (TFTs) used in liquid crystal display panels experience significant off-leakage currents, especially when exposed to light, leading to degradation in display image quality due to the inability to effectively reduce light leakage currents in existing solutions, which also increase manufacturing costs and decrease yield.
Innovation Solution
A TFT with a polycrystalline semiconductor layer on a substrate, featuring a gate electrode with a gate insulating film in between, and source/drain regions doped with impurities where the impurity concentration is set between 2.5×10^18/cm^3 to 5.5×10^18/cm^3 and the activation rate is between 1% to 7%, reducing off-leakage currents both in dark and light states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional polycrystalline silicon TFT is used with standard impurity concentration, then manufacturing process is simple, but off-leakage current is large causing image quality degradation
Solution Approach 1:
The patent applies parameter changes by precisely controlling the impurity concentration in source/drain regions to a specific range (5×10^19 to 1×10^21 atoms/cm³) and adjusting the annealing temperature (400-600°C) to achieve optimal impurity activation rate (1-7%). This parameter optimization reduces off-leakage current while maintaining compatibility with existing manufacturing processes, resolving the contradiction between reliability improvement and process complexity.
2Reliability
If additional processes are added to reduce off-leakage current, then light leakage current is reduced, but manufacturing cost increases and yield decreases
Solution Approach 1:
The patent merges the light leakage reduction function into the standard annealing process that is already required for impurity activation. By optimizing the annealing parameters (temperature range 400-600°C and time 1-120 minutes) to simultaneously achieve both impurity activation and light leakage current reduction, no additional separate process is needed. This integration maintains high manufacturing yield while achieving the reliability improvement.
3Reliability
If impurity concentration in source/drain regions is lowered to reduce off-leakage current, then tunneling is reduced, but ON-current may be insufficient
Solution Approach 1:
The patent applies local quality by creating a non-uniform impurity concentration distribution within the source/drain regions. The impurity concentration is optimized to a specific range (5×10^19 to 1×10^21 atoms/cm³) that provides the right balance: low enough to reduce tunneling and off-leakage current, but high enough to maintain sufficient ON-current. The localized control of impurity concentration and activation rate (1-7%) in the source/drain regions achieves this balance without affecting the channel region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively minimizes off-leakage currents in both dark and light conditions, preventing image quality degradation and simplifying the manufacturing process by maintaining existing procedures without additional complex steps, thus enhancing the reliability and efficiency of liquid crystal display panels.
Implementation Method 1
source/drain regions doped with an impurity formed in the semiconductor layer
Implementation Method 2
the activation rate of the impurity contained in the source/drain regions is within 1% to 7%
Data Source
AI summary
A thin film transistor (TFT) is provided which is capable of reducing leakage currents in a polycrystalline silicon TFT without causing an increase in manufacturing processes. Source/drain regions of an activated layer of the TFT to be formed in a circuit region and pixel region formed on a glass substrate of a liquid crystal display panel for a mobile phone is formed so that its boron impurity falls within a range of 2.5×1018/cm3 to 5.5×1018/cm3 and its impurity activation falls within a range of 1% to 7%.