Poly-1 Doping for Dual-Poly Flash Memory ESD Protection
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Solution Overview
Problem
In semiconductor manufacturing, the challenge lies in achieving effective electrostatic discharge (ESD) protection and uniform charge distribution during the dual-poly process, particularly in flash memory devices, where high resistance of the poly-1 layer hinders efficient charge transfer to passive components, leading to non-uniform charge distributions and potential device failures.
Innovation Solution
Doping the poly-1 layer prior to or concurrent with poly-2 deposition reduces its resistance, allowing for more effective charge transfer to passive components like low-voltage capacitors, thereby enhancing ESD protection and achieving uniform charge distribution across the semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the poly-1 layer is left undoped to maintain process simplicity, then the manufacturing process remains simple, but the resistance of the poly-1 layer remains high which prevents effective charge transfer to passive components
Solution Approach 1:
The poly-1 layer is doped with phosphorus or arsenic dopants before the formation of passive components (capacitors or diodes). This preliminary doping action ensures that the poly-1 layer has sufficient conductivity to effectively transfer charge to the passive components during subsequent processing steps, resolving the contradiction by preparing the charge transfer pathway in advance rather than adding complexity later
Solution Approach 2:
The electrical conductivity parameter of the poly-1 layer is changed through dopant implantation. By introducing dopants at controlled concentrations and depths, the resistance of the poly-1 layer is reduced from a high-resistance state to a low-resistance state, enabling effective charge transfer while maintaining process integration
2Reliability
If integrated passive components (capacitors, diodes) are added to improve ESD protection, then charge distribution improves, but the device complexity and manufacturing cost increase
Solution Approach 1:
The invention merges the charge transfer function with existing passive components (capacitors or diodes) that are already part of the flash memory device architecture. By doping the poly-1 layer to enable charge transfer to these existing components, the ESD protection function is achieved without adding separate dedicated ESD protection components, thus reducing device complexity while maintaining reliability
Solution Approach 2:
The passive components (capacitors or diodes) in the flash memory device are given a dual function: their original function (storage or rectification) plus an additional ESD protection function through the doped poly-1 layer charge transfer pathway. This multi-functionality approach improves ESD protection without requiring additional dedicated components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the conductivity of the poly-1 layer, reducing ESD events and ensuring more uniform charge distribution, which enhances the yield and reliability of semiconductor devices by providing robust charging protection and minimizing device failures during processing.
Implementation Method 1
doping the poly-1 layer concurrent with or prior to the poly-2 deposition
Data Source
AI summary
The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.