Polycrystalline Silicon Gate Doping for Lower Capacitance Thickness
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Solution Overview
Problem
Existing methods for increasing transistor capacitance by reducing gate dielectric layer thickness risk breakdown due to extreme thinness, and current techniques to reduce capacitance equivalent thickness are limited in effectiveness.
Innovation Solution
A method involving sequential stacking of a substrate, gate dielectric layer, and undoped polycrystalline silicon layer, followed by thermal doping and ion implantation to dope ions, allowing the concentration of doping ions to exceed solid solubility limits, thereby reducing depletion layer thickness and capacitance equivalent thickness, while improving ion diffusion rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the gate dielectric layer is reduced to increase transistor capacitance, then the capacitance size increases, but the risk of breakdown due to extreme thinness increases
Solution Approach 1:
The patent changes the doping concentration parameter in the polycrystalline silicon layer, doping ions to exceed solid solubility limits and form high-concentration regions. This parameter change reduces the depletion layer thickness without requiring reduction of the gate dielectric layer thickness, thereby increasing transistor capacitance while maintaining gate dielectric layer integrity and avoiding breakdown risks
Solution Approach 2:
The patent applies local quality by creating a high-concentration doping region in a preset area of the polycrystalline silicon layer through ion implantation. This localized high-concentration region specifically reduces the depletion layer thickness in the required area, achieving capacitance increase without uniformly thinning the gate dielectric layer throughout the entire structure
2Quantity of substance
If the thickness of the gate depletion layer is reduced to increase capacitance, then the capacitance equivalent thickness decreases, but the effectiveness is limited
Solution Approach 1:
The patent performs preliminary action by first conducting a thermal doping process to dope ions in the polycrystalline silicon layer, creating a foundation of doped regions. Subsequently, an ion implantation process is performed to add second doping ions in a preset region. This two-stage preliminary action sequence enables precise control over the depletion layer thickness and achieves superior capacitance equivalent thickness reduction compared to single-process methods
Solution Approach 2:
The patent uses composite materials by combining thermal doping and ion implantation processes to create a polycrystalline silicon layer with complex, multi-zone doping concentration distributions. This composite approach allows independent optimization of different regions, achieving precise depletion layer thickness control and effective capacitance equivalent thickness reduction that neither process could achieve alone
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases transistor capacitance while maintaining structural integrity by reducing depletion layer thickness and enhancing ion concentration near the gate dielectric layer, resulting in a larger capacitance with a smaller capacitance equivalent thickness.
Implementation Method 1
A thermal doping process is performed, and first doping ions are doped in the polycrystalline silicon layer
Implementation Method 2
An ion implantation process is performed, and second doping ions are doped in a preset region of the polycrystalline silicon layer
Implementation Method 3
improving ion diffusion rates
Data Source
AI summary
A method for forming a semiconductor structure includes: providing a substrate, a gate dielectric layer and an undoped polycrystalline silicon layer sequentially stacked; performing a thermal doping process, and doping first doping ions in the polycrystalline silicon layer; and performing an ion implantation process, and doping second doping ions in a preset region of the polycrystalline silicon layer. The preset region is spaced at a preset distance from a surface of the polycrystalline silicon layer away from the gate dielectric layer in a direction perpendicular to a surface of the substrate.